xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nv04_fbcon.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2009 Ben Skeggs
3*4882a593Smuzhiyun  * Copyright 2008 Stuart Bennett
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
13*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
14*4882a593Smuzhiyun  * Software.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19*4882a593Smuzhiyun  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20*4882a593Smuzhiyun  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21*4882a593Smuzhiyun  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #define NVIF_DEBUG_PRINT_DISABLE
25*4882a593Smuzhiyun #include "nouveau_drv.h"
26*4882a593Smuzhiyun #include "nouveau_dma.h"
27*4882a593Smuzhiyun #include "nouveau_fbcon.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include <nvif/push006c.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun int
nv04_fbcon_copyarea(struct fb_info * info,const struct fb_copyarea * region)32*4882a593Smuzhiyun nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	struct nouveau_fbdev *nfbdev = info->par;
35*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
36*4882a593Smuzhiyun 	struct nouveau_channel *chan = drm->channel;
37*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
38*4882a593Smuzhiyun 	int ret;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	ret = PUSH_WAIT(push, 4);
41*4882a593Smuzhiyun 	if (ret)
42*4882a593Smuzhiyun 		return ret;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV05F, 0x0300, (region->sy << 16) | region->sx,
45*4882a593Smuzhiyun 			       0x0304, (region->dy << 16) | region->dx,
46*4882a593Smuzhiyun 			       0x0308, (region->height << 16) | region->width);
47*4882a593Smuzhiyun 	PUSH_KICK(push);
48*4882a593Smuzhiyun 	return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun int
nv04_fbcon_fillrect(struct fb_info * info,const struct fb_fillrect * rect)52*4882a593Smuzhiyun nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	struct nouveau_fbdev *nfbdev = info->par;
55*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
56*4882a593Smuzhiyun 	struct nouveau_channel *chan = drm->channel;
57*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
58*4882a593Smuzhiyun 	int ret;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	ret = PUSH_WAIT(push, 7);
61*4882a593Smuzhiyun 	if (ret)
62*4882a593Smuzhiyun 		return ret;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x02fc, (rect->rop != ROP_COPY) ? 1 : 3);
65*4882a593Smuzhiyun 	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
66*4882a593Smuzhiyun 	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
67*4882a593Smuzhiyun 		PUSH_NVSQ(push, NV04A, 0x03fc, ((uint32_t *)info->pseudo_palette)[rect->color]);
68*4882a593Smuzhiyun 	else
69*4882a593Smuzhiyun 		PUSH_NVSQ(push, NV04A, 0x03fc, rect->color);
70*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0400, (rect->dx << 16) | rect->dy,
71*4882a593Smuzhiyun 			       0x0404, (rect->width << 16) | rect->height);
72*4882a593Smuzhiyun 	PUSH_KICK(push);
73*4882a593Smuzhiyun 	return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun int
nv04_fbcon_imageblit(struct fb_info * info,const struct fb_image * image)77*4882a593Smuzhiyun nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	struct nouveau_fbdev *nfbdev = info->par;
80*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
81*4882a593Smuzhiyun 	struct nouveau_channel *chan = drm->channel;
82*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
83*4882a593Smuzhiyun 	uint32_t fg;
84*4882a593Smuzhiyun 	uint32_t bg;
85*4882a593Smuzhiyun 	uint32_t dsize;
86*4882a593Smuzhiyun 	uint32_t *data = (uint32_t *)image->data;
87*4882a593Smuzhiyun 	int ret;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	if (image->depth != 1)
90*4882a593Smuzhiyun 		return -ENODEV;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	ret = PUSH_WAIT(push, 8);
93*4882a593Smuzhiyun 	if (ret)
94*4882a593Smuzhiyun 		return ret;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
97*4882a593Smuzhiyun 	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
98*4882a593Smuzhiyun 		fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
99*4882a593Smuzhiyun 		bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
100*4882a593Smuzhiyun 	} else {
101*4882a593Smuzhiyun 		fg = image->fg_color;
102*4882a593Smuzhiyun 		bg = image->bg_color;
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0be4, (image->dy << 16) | (image->dx & 0xffff),
106*4882a593Smuzhiyun 			       0x0be8, ((image->dy + image->height) << 16) |
107*4882a593Smuzhiyun 				       ((image->dx + image->width) & 0xffff),
108*4882a593Smuzhiyun 			       0x0bec, bg,
109*4882a593Smuzhiyun 			       0x0bf0, fg,
110*4882a593Smuzhiyun 			       0x0bf4, (image->height << 16) | ALIGN(image->width, 8),
111*4882a593Smuzhiyun 			       0x0bf8, (image->height << 16) | image->width,
112*4882a593Smuzhiyun 			       0x0bfc, (image->dy << 16) | (image->dx & 0xffff));
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
115*4882a593Smuzhiyun 	while (dsize) {
116*4882a593Smuzhiyun 		int iter_len = dsize > 128 ? 128 : dsize;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 		ret = PUSH_WAIT(push, iter_len + 1);
119*4882a593Smuzhiyun 		if (ret)
120*4882a593Smuzhiyun 			return ret;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 		PUSH_NVSQ(push, NV04A, 0x0c00, data, iter_len);
123*4882a593Smuzhiyun 		data += iter_len;
124*4882a593Smuzhiyun 		dsize -= iter_len;
125*4882a593Smuzhiyun 	}
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	PUSH_KICK(push);
128*4882a593Smuzhiyun 	return 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun int
nv04_fbcon_accel_init(struct fb_info * info)132*4882a593Smuzhiyun nv04_fbcon_accel_init(struct fb_info *info)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	struct nouveau_fbdev *nfbdev = info->par;
135*4882a593Smuzhiyun 	struct drm_device *dev = nfbdev->helper.dev;
136*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
137*4882a593Smuzhiyun 	struct nouveau_channel *chan = drm->channel;
138*4882a593Smuzhiyun 	struct nvif_device *device = &drm->client.device;
139*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
140*4882a593Smuzhiyun 	int surface_fmt, pattern_fmt, rect_fmt;
141*4882a593Smuzhiyun 	int ret;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	switch (info->var.bits_per_pixel) {
144*4882a593Smuzhiyun 	case 8:
145*4882a593Smuzhiyun 		surface_fmt = 1;
146*4882a593Smuzhiyun 		pattern_fmt = 3;
147*4882a593Smuzhiyun 		rect_fmt = 3;
148*4882a593Smuzhiyun 		break;
149*4882a593Smuzhiyun 	case 16:
150*4882a593Smuzhiyun 		surface_fmt = 4;
151*4882a593Smuzhiyun 		pattern_fmt = 1;
152*4882a593Smuzhiyun 		rect_fmt = 1;
153*4882a593Smuzhiyun 		break;
154*4882a593Smuzhiyun 	case 32:
155*4882a593Smuzhiyun 		switch (info->var.transp.length) {
156*4882a593Smuzhiyun 		case 0: /* depth 24 */
157*4882a593Smuzhiyun 		case 8: /* depth 32 */
158*4882a593Smuzhiyun 			break;
159*4882a593Smuzhiyun 		default:
160*4882a593Smuzhiyun 			return -EINVAL;
161*4882a593Smuzhiyun 		}
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 		surface_fmt = 6;
164*4882a593Smuzhiyun 		pattern_fmt = 3;
165*4882a593Smuzhiyun 		rect_fmt = 3;
166*4882a593Smuzhiyun 		break;
167*4882a593Smuzhiyun 	default:
168*4882a593Smuzhiyun 		return -EINVAL;
169*4882a593Smuzhiyun 	}
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconCtxSurf2d", 0x0062,
172*4882a593Smuzhiyun 			       device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
173*4882a593Smuzhiyun 			       0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
174*4882a593Smuzhiyun 	if (ret)
175*4882a593Smuzhiyun 		return ret;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconCtxClip", 0x0019, 0x0019,
178*4882a593Smuzhiyun 			       NULL, 0, &nfbdev->clip);
179*4882a593Smuzhiyun 	if (ret)
180*4882a593Smuzhiyun 		return ret;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconCtxRop", 0x0043, 0x0043,
183*4882a593Smuzhiyun 			       NULL, 0, &nfbdev->rop);
184*4882a593Smuzhiyun 	if (ret)
185*4882a593Smuzhiyun 		return ret;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconCtxPatt", 0x0044, 0x0044,
188*4882a593Smuzhiyun 			       NULL, 0, &nfbdev->patt);
189*4882a593Smuzhiyun 	if (ret)
190*4882a593Smuzhiyun 		return ret;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconGdiRectText", 0x004a, 0x004a,
193*4882a593Smuzhiyun 			       NULL, 0, &nfbdev->gdi);
194*4882a593Smuzhiyun 	if (ret)
195*4882a593Smuzhiyun 		return ret;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	ret = nvif_object_ctor(&chan->user, "fbconImageBlit", 0x005f,
198*4882a593Smuzhiyun 			       device->info.chipset >= 0x11 ? 0x009f : 0x005f,
199*4882a593Smuzhiyun 			       NULL, 0, &nfbdev->blit);
200*4882a593Smuzhiyun 	if (ret)
201*4882a593Smuzhiyun 		return ret;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	if (PUSH_WAIT(push, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
204*4882a593Smuzhiyun 		nouveau_fbcon_gpu_lockup(info);
205*4882a593Smuzhiyun 		return 0;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV042, 0x0000, nfbdev->surf2d.handle);
209*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV042, 0x0184, chan->vram.handle,
210*4882a593Smuzhiyun 			       0x0188, chan->vram.handle);
211*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV042, 0x0300, surface_fmt,
212*4882a593Smuzhiyun 			       0x0304, info->fix.line_length | (info->fix.line_length << 16),
213*4882a593Smuzhiyun 			       0x0308, info->fix.smem_start - dev->mode_config.fb_base,
214*4882a593Smuzhiyun 			       0x030c, info->fix.smem_start - dev->mode_config.fb_base);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV043, 0x0000, nfbdev->rop.handle);
217*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV043, 0x0300, 0x55);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV044, 0x0000, nfbdev->patt.handle);
220*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV044, 0x0300, pattern_fmt,
221*4882a593Smuzhiyun #ifdef __BIG_ENDIAN
222*4882a593Smuzhiyun 			       0x0304, 2,
223*4882a593Smuzhiyun #else
224*4882a593Smuzhiyun 			       0x0304, 1,
225*4882a593Smuzhiyun #endif
226*4882a593Smuzhiyun 			       0x0308, 0,
227*4882a593Smuzhiyun 			       0x030c, 1,
228*4882a593Smuzhiyun 			       0x0310, ~0,
229*4882a593Smuzhiyun 			       0x0314, ~0,
230*4882a593Smuzhiyun 			       0x0318, ~0,
231*4882a593Smuzhiyun 			       0x031c, ~0);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV019, 0x0000, nfbdev->clip.handle);
234*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV019, 0x0300, 0,
235*4882a593Smuzhiyun 			       0x0304, (info->var.yres_virtual << 16) | info->var.xres_virtual);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV05F, 0x0000, nfbdev->blit.handle);
238*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV05F, 0x019c, nfbdev->surf2d.handle);
239*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV05F, 0x02fc, 3);
240*4882a593Smuzhiyun 	if (nfbdev->blit.oclass == 0x009f) {
241*4882a593Smuzhiyun 		PUSH_NVSQ(push, NV09F, 0x0120, 0,
242*4882a593Smuzhiyun 				       0x0124, 1,
243*4882a593Smuzhiyun 				       0x0128, 2);
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0000, nfbdev->gdi.handle);
247*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0198, nfbdev->surf2d.handle);
248*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0188, nfbdev->patt.handle,
249*4882a593Smuzhiyun 			       0x018c, nfbdev->rop.handle);
250*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0304, 1);
251*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x0300, rect_fmt);
252*4882a593Smuzhiyun 	PUSH_NVSQ(push, NV04A, 0x02fc, 3);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	PUSH_KICK(push);
255*4882a593Smuzhiyun 	return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
258