xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nouveau_hwmon.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2010 Red Hat Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Authors: Ben Skeggs
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #ifdef CONFIG_ACPI
26*4882a593Smuzhiyun #include <linux/acpi.h>
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun #include <linux/power_supply.h>
29*4882a593Smuzhiyun #include <linux/hwmon.h>
30*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include "nouveau_drv.h"
33*4882a593Smuzhiyun #include "nouveau_hwmon.h"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include <nvkm/subdev/iccsense.h>
36*4882a593Smuzhiyun #include <nvkm/subdev/volt.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_show_temp1_auto_point1_pwm(struct device * d,struct device_attribute * a,char * buf)41*4882a593Smuzhiyun nouveau_hwmon_show_temp1_auto_point1_pwm(struct device *d,
42*4882a593Smuzhiyun 					 struct device_attribute *a, char *buf)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n", 100);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR(temp1_auto_point1_pwm, 0444,
47*4882a593Smuzhiyun 			  nouveau_hwmon_show_temp1_auto_point1_pwm, NULL, 0);
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_temp1_auto_point1_temp(struct device * d,struct device_attribute * a,char * buf)50*4882a593Smuzhiyun nouveau_hwmon_temp1_auto_point1_temp(struct device *d,
51*4882a593Smuzhiyun 				     struct device_attribute *a, char *buf)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
54*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
55*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n",
58*4882a593Smuzhiyun 	      therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST) * 1000);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_set_temp1_auto_point1_temp(struct device * d,struct device_attribute * a,const char * buf,size_t count)61*4882a593Smuzhiyun nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d,
62*4882a593Smuzhiyun 					 struct device_attribute *a,
63*4882a593Smuzhiyun 					 const char *buf, size_t count)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
66*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
67*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
68*4882a593Smuzhiyun 	long value;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	if (kstrtol(buf, 10, &value))
71*4882a593Smuzhiyun 		return -EINVAL;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST,
74*4882a593Smuzhiyun 			value / 1000);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return count;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp, 0644,
79*4882a593Smuzhiyun 			  nouveau_hwmon_temp1_auto_point1_temp,
80*4882a593Smuzhiyun 			  nouveau_hwmon_set_temp1_auto_point1_temp, 0);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device * d,struct device_attribute * a,char * buf)83*4882a593Smuzhiyun nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d,
84*4882a593Smuzhiyun 					  struct device_attribute *a, char *buf)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
87*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
88*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n",
91*4882a593Smuzhiyun 	 therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device * d,struct device_attribute * a,const char * buf,size_t count)94*4882a593Smuzhiyun nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d,
95*4882a593Smuzhiyun 					      struct device_attribute *a,
96*4882a593Smuzhiyun 					      const char *buf, size_t count)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
99*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
100*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
101*4882a593Smuzhiyun 	long value;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	if (kstrtol(buf, 10, &value))
104*4882a593Smuzhiyun 		return -EINVAL;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST,
107*4882a593Smuzhiyun 			value / 1000);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return count;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp_hyst, 0644,
112*4882a593Smuzhiyun 			  nouveau_hwmon_temp1_auto_point1_temp_hyst,
113*4882a593Smuzhiyun 			  nouveau_hwmon_set_temp1_auto_point1_temp_hyst, 0);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_get_pwm1_max(struct device * d,struct device_attribute * a,char * buf)116*4882a593Smuzhiyun nouveau_hwmon_get_pwm1_max(struct device *d,
117*4882a593Smuzhiyun 			   struct device_attribute *a, char *buf)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
120*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
121*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
122*4882a593Smuzhiyun 	int ret;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY);
125*4882a593Smuzhiyun 	if (ret < 0)
126*4882a593Smuzhiyun 		return ret;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return sprintf(buf, "%i\n", ret);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_get_pwm1_min(struct device * d,struct device_attribute * a,char * buf)132*4882a593Smuzhiyun nouveau_hwmon_get_pwm1_min(struct device *d,
133*4882a593Smuzhiyun 			   struct device_attribute *a, char *buf)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
136*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
137*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
138*4882a593Smuzhiyun 	int ret;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY);
141*4882a593Smuzhiyun 	if (ret < 0)
142*4882a593Smuzhiyun 		return ret;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	return sprintf(buf, "%i\n", ret);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_set_pwm1_min(struct device * d,struct device_attribute * a,const char * buf,size_t count)148*4882a593Smuzhiyun nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a,
149*4882a593Smuzhiyun 			   const char *buf, size_t count)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
152*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
153*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
154*4882a593Smuzhiyun 	long value;
155*4882a593Smuzhiyun 	int ret;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	if (kstrtol(buf, 10, &value))
158*4882a593Smuzhiyun 		return -EINVAL;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY, value);
161*4882a593Smuzhiyun 	if (ret < 0)
162*4882a593Smuzhiyun 		return ret;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	return count;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR(pwm1_min, 0644,
167*4882a593Smuzhiyun 			  nouveau_hwmon_get_pwm1_min,
168*4882a593Smuzhiyun 			  nouveau_hwmon_set_pwm1_min, 0);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static ssize_t
nouveau_hwmon_set_pwm1_max(struct device * d,struct device_attribute * a,const char * buf,size_t count)171*4882a593Smuzhiyun nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a,
172*4882a593Smuzhiyun 			   const char *buf, size_t count)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	struct drm_device *dev = dev_get_drvdata(d);
175*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
176*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
177*4882a593Smuzhiyun 	long value;
178*4882a593Smuzhiyun 	int ret;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	if (kstrtol(buf, 10, &value))
181*4882a593Smuzhiyun 		return -EINVAL;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY, value);
184*4882a593Smuzhiyun 	if (ret < 0)
185*4882a593Smuzhiyun 		return ret;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	return count;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR(pwm1_max, 0644,
190*4882a593Smuzhiyun 			  nouveau_hwmon_get_pwm1_max,
191*4882a593Smuzhiyun 			  nouveau_hwmon_set_pwm1_max, 0);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static struct attribute *pwm_fan_sensor_attrs[] = {
194*4882a593Smuzhiyun 	&sensor_dev_attr_pwm1_min.dev_attr.attr,
195*4882a593Smuzhiyun 	&sensor_dev_attr_pwm1_max.dev_attr.attr,
196*4882a593Smuzhiyun 	NULL
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun static const struct attribute_group pwm_fan_sensor_group = {
199*4882a593Smuzhiyun 	.attrs = pwm_fan_sensor_attrs,
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static struct attribute *temp1_auto_point_sensor_attrs[] = {
203*4882a593Smuzhiyun 	&sensor_dev_attr_temp1_auto_point1_pwm.dev_attr.attr,
204*4882a593Smuzhiyun 	&sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr,
205*4882a593Smuzhiyun 	&sensor_dev_attr_temp1_auto_point1_temp_hyst.dev_attr.attr,
206*4882a593Smuzhiyun 	NULL
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun static const struct attribute_group temp1_auto_point_sensor_group = {
209*4882a593Smuzhiyun 	.attrs = temp1_auto_point_sensor_attrs,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun #define N_ATTR_GROUPS   3
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static const u32 nouveau_config_chip[] = {
215*4882a593Smuzhiyun 	HWMON_C_UPDATE_INTERVAL,
216*4882a593Smuzhiyun 	0
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun static const u32 nouveau_config_in[] = {
220*4882a593Smuzhiyun 	HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_LABEL,
221*4882a593Smuzhiyun 	0
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static const u32 nouveau_config_temp[] = {
225*4882a593Smuzhiyun 	HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
226*4882a593Smuzhiyun 	HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_EMERGENCY |
227*4882a593Smuzhiyun 	HWMON_T_EMERGENCY_HYST,
228*4882a593Smuzhiyun 	0
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun static const u32 nouveau_config_fan[] = {
232*4882a593Smuzhiyun 	HWMON_F_INPUT,
233*4882a593Smuzhiyun 	0
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const u32 nouveau_config_pwm[] = {
237*4882a593Smuzhiyun 	HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
238*4882a593Smuzhiyun 	0
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static const u32 nouveau_config_power[] = {
242*4882a593Smuzhiyun 	HWMON_P_INPUT | HWMON_P_CAP_MAX | HWMON_P_CRIT,
243*4882a593Smuzhiyun 	0
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_chip = {
247*4882a593Smuzhiyun 	.type = hwmon_chip,
248*4882a593Smuzhiyun 	.config = nouveau_config_chip,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_temp = {
252*4882a593Smuzhiyun 	.type = hwmon_temp,
253*4882a593Smuzhiyun 	.config = nouveau_config_temp,
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_fan = {
257*4882a593Smuzhiyun 	.type = hwmon_fan,
258*4882a593Smuzhiyun 	.config = nouveau_config_fan,
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_in = {
262*4882a593Smuzhiyun 	.type = hwmon_in,
263*4882a593Smuzhiyun 	.config = nouveau_config_in,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_pwm = {
267*4882a593Smuzhiyun 	.type = hwmon_pwm,
268*4882a593Smuzhiyun 	.config = nouveau_config_pwm,
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static const struct hwmon_channel_info nouveau_power = {
272*4882a593Smuzhiyun 	.type = hwmon_power,
273*4882a593Smuzhiyun 	.config = nouveau_config_power,
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun static const struct hwmon_channel_info *nouveau_info[] = {
277*4882a593Smuzhiyun 	&nouveau_chip,
278*4882a593Smuzhiyun 	&nouveau_temp,
279*4882a593Smuzhiyun 	&nouveau_fan,
280*4882a593Smuzhiyun 	&nouveau_in,
281*4882a593Smuzhiyun 	&nouveau_pwm,
282*4882a593Smuzhiyun 	&nouveau_power,
283*4882a593Smuzhiyun 	NULL
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun static umode_t
nouveau_chip_is_visible(const void * data,u32 attr,int channel)287*4882a593Smuzhiyun nouveau_chip_is_visible(const void *data, u32 attr, int channel)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	switch (attr) {
290*4882a593Smuzhiyun 	case hwmon_chip_update_interval:
291*4882a593Smuzhiyun 		return 0444;
292*4882a593Smuzhiyun 	default:
293*4882a593Smuzhiyun 		return 0;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun static umode_t
nouveau_power_is_visible(const void * data,u32 attr,int channel)298*4882a593Smuzhiyun nouveau_power_is_visible(const void *data, u32 attr, int channel)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data);
301*4882a593Smuzhiyun 	struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	if (!iccsense || !iccsense->data_valid || list_empty(&iccsense->rails))
304*4882a593Smuzhiyun 		return 0;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	switch (attr) {
307*4882a593Smuzhiyun 	case hwmon_power_input:
308*4882a593Smuzhiyun 		return 0444;
309*4882a593Smuzhiyun 	case hwmon_power_max:
310*4882a593Smuzhiyun 		if (iccsense->power_w_max)
311*4882a593Smuzhiyun 			return 0444;
312*4882a593Smuzhiyun 		return 0;
313*4882a593Smuzhiyun 	case hwmon_power_crit:
314*4882a593Smuzhiyun 		if (iccsense->power_w_crit)
315*4882a593Smuzhiyun 			return 0444;
316*4882a593Smuzhiyun 		return 0;
317*4882a593Smuzhiyun 	default:
318*4882a593Smuzhiyun 		return 0;
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun static umode_t
nouveau_temp_is_visible(const void * data,u32 attr,int channel)323*4882a593Smuzhiyun nouveau_temp_is_visible(const void *data, u32 attr, int channel)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data);
326*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	if (!therm || !therm->attr_get || nvkm_therm_temp_get(therm) < 0)
329*4882a593Smuzhiyun 		return 0;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	switch (attr) {
332*4882a593Smuzhiyun 	case hwmon_temp_input:
333*4882a593Smuzhiyun 		return 0444;
334*4882a593Smuzhiyun 	case hwmon_temp_max:
335*4882a593Smuzhiyun 	case hwmon_temp_max_hyst:
336*4882a593Smuzhiyun 	case hwmon_temp_crit:
337*4882a593Smuzhiyun 	case hwmon_temp_crit_hyst:
338*4882a593Smuzhiyun 	case hwmon_temp_emergency:
339*4882a593Smuzhiyun 	case hwmon_temp_emergency_hyst:
340*4882a593Smuzhiyun 		return 0644;
341*4882a593Smuzhiyun 	default:
342*4882a593Smuzhiyun 		return 0;
343*4882a593Smuzhiyun 	}
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun static umode_t
nouveau_pwm_is_visible(const void * data,u32 attr,int channel)347*4882a593Smuzhiyun nouveau_pwm_is_visible(const void *data, u32 attr, int channel)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data);
350*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	if (!therm || !therm->attr_get || !therm->fan_get ||
353*4882a593Smuzhiyun 	    therm->fan_get(therm) < 0)
354*4882a593Smuzhiyun 		return 0;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	switch (attr) {
357*4882a593Smuzhiyun 	case hwmon_pwm_enable:
358*4882a593Smuzhiyun 	case hwmon_pwm_input:
359*4882a593Smuzhiyun 		return 0644;
360*4882a593Smuzhiyun 	default:
361*4882a593Smuzhiyun 		return 0;
362*4882a593Smuzhiyun 	}
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun static umode_t
nouveau_input_is_visible(const void * data,u32 attr,int channel)366*4882a593Smuzhiyun nouveau_input_is_visible(const void *data, u32 attr, int channel)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data);
369*4882a593Smuzhiyun 	struct nvkm_volt *volt = nvxx_volt(&drm->client.device);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	if (!volt || nvkm_volt_get(volt) < 0)
372*4882a593Smuzhiyun 		return 0;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	switch (attr) {
375*4882a593Smuzhiyun 	case hwmon_in_input:
376*4882a593Smuzhiyun 	case hwmon_in_label:
377*4882a593Smuzhiyun 	case hwmon_in_min:
378*4882a593Smuzhiyun 	case hwmon_in_max:
379*4882a593Smuzhiyun 		return 0444;
380*4882a593Smuzhiyun 	default:
381*4882a593Smuzhiyun 		return 0;
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun static umode_t
nouveau_fan_is_visible(const void * data,u32 attr,int channel)386*4882a593Smuzhiyun nouveau_fan_is_visible(const void *data, u32 attr, int channel)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data);
389*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	if (!therm || !therm->attr_get || nvkm_therm_fan_sense(therm) < 0)
392*4882a593Smuzhiyun 		return 0;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	switch (attr) {
395*4882a593Smuzhiyun 	case hwmon_fan_input:
396*4882a593Smuzhiyun 		return 0444;
397*4882a593Smuzhiyun 	default:
398*4882a593Smuzhiyun 		return 0;
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun static int
nouveau_chip_read(struct device * dev,u32 attr,int channel,long * val)403*4882a593Smuzhiyun nouveau_chip_read(struct device *dev, u32 attr, int channel, long *val)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	switch (attr) {
406*4882a593Smuzhiyun 	case hwmon_chip_update_interval:
407*4882a593Smuzhiyun 		*val = 1000;
408*4882a593Smuzhiyun 		break;
409*4882a593Smuzhiyun 	default:
410*4882a593Smuzhiyun 		return -EOPNOTSUPP;
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	return 0;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun static int
nouveau_temp_read(struct device * dev,u32 attr,int channel,long * val)417*4882a593Smuzhiyun nouveau_temp_read(struct device *dev, u32 attr, int channel, long *val)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
420*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
421*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
422*4882a593Smuzhiyun 	int ret;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	if (!therm || !therm->attr_get)
425*4882a593Smuzhiyun 		return -EOPNOTSUPP;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	switch (attr) {
428*4882a593Smuzhiyun 	case hwmon_temp_input:
429*4882a593Smuzhiyun 		if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON)
430*4882a593Smuzhiyun 			return -EINVAL;
431*4882a593Smuzhiyun 		ret = nvkm_therm_temp_get(therm);
432*4882a593Smuzhiyun 		*val = ret < 0 ? ret : (ret * 1000);
433*4882a593Smuzhiyun 		break;
434*4882a593Smuzhiyun 	case hwmon_temp_max:
435*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK)
436*4882a593Smuzhiyun 					* 1000;
437*4882a593Smuzhiyun 		break;
438*4882a593Smuzhiyun 	case hwmon_temp_max_hyst:
439*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST)
440*4882a593Smuzhiyun 					* 1000;
441*4882a593Smuzhiyun 		break;
442*4882a593Smuzhiyun 	case hwmon_temp_crit:
443*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL)
444*4882a593Smuzhiyun 					* 1000;
445*4882a593Smuzhiyun 		break;
446*4882a593Smuzhiyun 	case hwmon_temp_crit_hyst:
447*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST)
448*4882a593Smuzhiyun 					* 1000;
449*4882a593Smuzhiyun 		break;
450*4882a593Smuzhiyun 	case hwmon_temp_emergency:
451*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN)
452*4882a593Smuzhiyun 					* 1000;
453*4882a593Smuzhiyun 		break;
454*4882a593Smuzhiyun 	case hwmon_temp_emergency_hyst:
455*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST)
456*4882a593Smuzhiyun 					* 1000;
457*4882a593Smuzhiyun 		break;
458*4882a593Smuzhiyun 	default:
459*4882a593Smuzhiyun 		return -EOPNOTSUPP;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	return 0;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun static int
nouveau_fan_read(struct device * dev,u32 attr,int channel,long * val)466*4882a593Smuzhiyun nouveau_fan_read(struct device *dev, u32 attr, int channel, long *val)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
469*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
470*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	if (!therm)
473*4882a593Smuzhiyun 		return -EOPNOTSUPP;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	switch (attr) {
476*4882a593Smuzhiyun 	case hwmon_fan_input:
477*4882a593Smuzhiyun 		if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON)
478*4882a593Smuzhiyun 			return -EINVAL;
479*4882a593Smuzhiyun 		*val = nvkm_therm_fan_sense(therm);
480*4882a593Smuzhiyun 		break;
481*4882a593Smuzhiyun 	default:
482*4882a593Smuzhiyun 		return -EOPNOTSUPP;
483*4882a593Smuzhiyun 	}
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	return 0;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun static int
nouveau_in_read(struct device * dev,u32 attr,int channel,long * val)489*4882a593Smuzhiyun nouveau_in_read(struct device *dev, u32 attr, int channel, long *val)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
492*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
493*4882a593Smuzhiyun 	struct nvkm_volt *volt = nvxx_volt(&drm->client.device);
494*4882a593Smuzhiyun 	int ret;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	if (!volt)
497*4882a593Smuzhiyun 		return -EOPNOTSUPP;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	switch (attr) {
500*4882a593Smuzhiyun 	case hwmon_in_input:
501*4882a593Smuzhiyun 		if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON)
502*4882a593Smuzhiyun 			return -EINVAL;
503*4882a593Smuzhiyun 		ret = nvkm_volt_get(volt);
504*4882a593Smuzhiyun 		*val = ret < 0 ? ret : (ret / 1000);
505*4882a593Smuzhiyun 		break;
506*4882a593Smuzhiyun 	case hwmon_in_min:
507*4882a593Smuzhiyun 		*val = volt->min_uv > 0 ? (volt->min_uv / 1000) : -ENODEV;
508*4882a593Smuzhiyun 		break;
509*4882a593Smuzhiyun 	case hwmon_in_max:
510*4882a593Smuzhiyun 		*val = volt->max_uv > 0 ? (volt->max_uv / 1000) : -ENODEV;
511*4882a593Smuzhiyun 		break;
512*4882a593Smuzhiyun 	default:
513*4882a593Smuzhiyun 		return -EOPNOTSUPP;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	return 0;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun static int
nouveau_pwm_read(struct device * dev,u32 attr,int channel,long * val)520*4882a593Smuzhiyun nouveau_pwm_read(struct device *dev, u32 attr, int channel, long *val)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
523*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
524*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	if (!therm || !therm->attr_get || !therm->fan_get)
527*4882a593Smuzhiyun 		return -EOPNOTSUPP;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	switch (attr) {
530*4882a593Smuzhiyun 	case hwmon_pwm_enable:
531*4882a593Smuzhiyun 		*val = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE);
532*4882a593Smuzhiyun 		break;
533*4882a593Smuzhiyun 	case hwmon_pwm_input:
534*4882a593Smuzhiyun 		if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON)
535*4882a593Smuzhiyun 			return -EINVAL;
536*4882a593Smuzhiyun 		*val = therm->fan_get(therm);
537*4882a593Smuzhiyun 		break;
538*4882a593Smuzhiyun 	default:
539*4882a593Smuzhiyun 		return -EOPNOTSUPP;
540*4882a593Smuzhiyun 	}
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	return 0;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun static int
nouveau_power_read(struct device * dev,u32 attr,int channel,long * val)546*4882a593Smuzhiyun nouveau_power_read(struct device *dev, u32 attr, int channel, long *val)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
549*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
550*4882a593Smuzhiyun 	struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	if (!iccsense)
553*4882a593Smuzhiyun 		return -EOPNOTSUPP;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	switch (attr) {
556*4882a593Smuzhiyun 	case hwmon_power_input:
557*4882a593Smuzhiyun 		if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON)
558*4882a593Smuzhiyun 			return -EINVAL;
559*4882a593Smuzhiyun 		*val = nvkm_iccsense_read_all(iccsense);
560*4882a593Smuzhiyun 		break;
561*4882a593Smuzhiyun 	case hwmon_power_max:
562*4882a593Smuzhiyun 		*val = iccsense->power_w_max;
563*4882a593Smuzhiyun 		break;
564*4882a593Smuzhiyun 	case hwmon_power_crit:
565*4882a593Smuzhiyun 		*val = iccsense->power_w_crit;
566*4882a593Smuzhiyun 		break;
567*4882a593Smuzhiyun 	default:
568*4882a593Smuzhiyun 		return -EOPNOTSUPP;
569*4882a593Smuzhiyun 	}
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	return 0;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun static int
nouveau_temp_write(struct device * dev,u32 attr,int channel,long val)575*4882a593Smuzhiyun nouveau_temp_write(struct device *dev, u32 attr, int channel, long val)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
578*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
579*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	if (!therm || !therm->attr_set)
582*4882a593Smuzhiyun 		return -EOPNOTSUPP;
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	switch (attr) {
585*4882a593Smuzhiyun 	case hwmon_temp_max:
586*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK,
587*4882a593Smuzhiyun 					val / 1000);
588*4882a593Smuzhiyun 	case hwmon_temp_max_hyst:
589*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST,
590*4882a593Smuzhiyun 					val / 1000);
591*4882a593Smuzhiyun 	case hwmon_temp_crit:
592*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL,
593*4882a593Smuzhiyun 					val / 1000);
594*4882a593Smuzhiyun 	case hwmon_temp_crit_hyst:
595*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST,
596*4882a593Smuzhiyun 					val / 1000);
597*4882a593Smuzhiyun 	case hwmon_temp_emergency:
598*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN,
599*4882a593Smuzhiyun 					val / 1000);
600*4882a593Smuzhiyun 	case hwmon_temp_emergency_hyst:
601*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST,
602*4882a593Smuzhiyun 					val / 1000);
603*4882a593Smuzhiyun 	default:
604*4882a593Smuzhiyun 		return -EOPNOTSUPP;
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun static int
nouveau_pwm_write(struct device * dev,u32 attr,int channel,long val)609*4882a593Smuzhiyun nouveau_pwm_write(struct device *dev, u32 attr, int channel, long val)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun 	struct drm_device *drm_dev = dev_get_drvdata(dev);
612*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(drm_dev);
613*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	if (!therm || !therm->attr_set)
616*4882a593Smuzhiyun 		return -EOPNOTSUPP;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	switch (attr) {
619*4882a593Smuzhiyun 	case hwmon_pwm_input:
620*4882a593Smuzhiyun 		return therm->fan_set(therm, val);
621*4882a593Smuzhiyun 	case hwmon_pwm_enable:
622*4882a593Smuzhiyun 		return therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MODE, val);
623*4882a593Smuzhiyun 	default:
624*4882a593Smuzhiyun 		return -EOPNOTSUPP;
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun static umode_t
nouveau_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)629*4882a593Smuzhiyun nouveau_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
630*4882a593Smuzhiyun 			int channel)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	switch (type) {
633*4882a593Smuzhiyun 	case hwmon_chip:
634*4882a593Smuzhiyun 		return nouveau_chip_is_visible(data, attr, channel);
635*4882a593Smuzhiyun 	case hwmon_temp:
636*4882a593Smuzhiyun 		return nouveau_temp_is_visible(data, attr, channel);
637*4882a593Smuzhiyun 	case hwmon_fan:
638*4882a593Smuzhiyun 		return nouveau_fan_is_visible(data, attr, channel);
639*4882a593Smuzhiyun 	case hwmon_in:
640*4882a593Smuzhiyun 		return nouveau_input_is_visible(data, attr, channel);
641*4882a593Smuzhiyun 	case hwmon_pwm:
642*4882a593Smuzhiyun 		return nouveau_pwm_is_visible(data, attr, channel);
643*4882a593Smuzhiyun 	case hwmon_power:
644*4882a593Smuzhiyun 		return nouveau_power_is_visible(data, attr, channel);
645*4882a593Smuzhiyun 	default:
646*4882a593Smuzhiyun 		return 0;
647*4882a593Smuzhiyun 	}
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun static const char input_label[] = "GPU core";
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun static int
nouveau_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** buf)653*4882a593Smuzhiyun nouveau_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
654*4882a593Smuzhiyun 		    int channel, const char **buf)
655*4882a593Smuzhiyun {
656*4882a593Smuzhiyun 	if (type == hwmon_in && attr == hwmon_in_label) {
657*4882a593Smuzhiyun 		*buf = input_label;
658*4882a593Smuzhiyun 		return 0;
659*4882a593Smuzhiyun 	}
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	return -EOPNOTSUPP;
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun static int
nouveau_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)665*4882a593Smuzhiyun nouveau_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
666*4882a593Smuzhiyun 							int channel, long *val)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	switch (type) {
669*4882a593Smuzhiyun 	case hwmon_chip:
670*4882a593Smuzhiyun 		return nouveau_chip_read(dev, attr, channel, val);
671*4882a593Smuzhiyun 	case hwmon_temp:
672*4882a593Smuzhiyun 		return nouveau_temp_read(dev, attr, channel, val);
673*4882a593Smuzhiyun 	case hwmon_fan:
674*4882a593Smuzhiyun 		return nouveau_fan_read(dev, attr, channel, val);
675*4882a593Smuzhiyun 	case hwmon_in:
676*4882a593Smuzhiyun 		return nouveau_in_read(dev, attr, channel, val);
677*4882a593Smuzhiyun 	case hwmon_pwm:
678*4882a593Smuzhiyun 		return nouveau_pwm_read(dev, attr, channel, val);
679*4882a593Smuzhiyun 	case hwmon_power:
680*4882a593Smuzhiyun 		return nouveau_power_read(dev, attr, channel, val);
681*4882a593Smuzhiyun 	default:
682*4882a593Smuzhiyun 		return -EOPNOTSUPP;
683*4882a593Smuzhiyun 	}
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun static int
nouveau_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)687*4882a593Smuzhiyun nouveau_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
688*4882a593Smuzhiyun 							int channel, long val)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun 	switch (type) {
691*4882a593Smuzhiyun 	case hwmon_temp:
692*4882a593Smuzhiyun 		return nouveau_temp_write(dev, attr, channel, val);
693*4882a593Smuzhiyun 	case hwmon_pwm:
694*4882a593Smuzhiyun 		return nouveau_pwm_write(dev, attr, channel, val);
695*4882a593Smuzhiyun 	default:
696*4882a593Smuzhiyun 		return -EOPNOTSUPP;
697*4882a593Smuzhiyun 	}
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun static const struct hwmon_ops nouveau_hwmon_ops = {
701*4882a593Smuzhiyun 	.is_visible = nouveau_is_visible,
702*4882a593Smuzhiyun 	.read = nouveau_read,
703*4882a593Smuzhiyun 	.read_string = nouveau_read_string,
704*4882a593Smuzhiyun 	.write = nouveau_write,
705*4882a593Smuzhiyun };
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun static const struct hwmon_chip_info nouveau_chip_info = {
708*4882a593Smuzhiyun 	.ops = &nouveau_hwmon_ops,
709*4882a593Smuzhiyun 	.info = nouveau_info,
710*4882a593Smuzhiyun };
711*4882a593Smuzhiyun #endif
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun int
nouveau_hwmon_init(struct drm_device * dev)714*4882a593Smuzhiyun nouveau_hwmon_init(struct drm_device *dev)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
717*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
718*4882a593Smuzhiyun 	struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device);
719*4882a593Smuzhiyun 	struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
720*4882a593Smuzhiyun 	struct nvkm_volt *volt = nvxx_volt(&drm->client.device);
721*4882a593Smuzhiyun 	const struct attribute_group *special_groups[N_ATTR_GROUPS];
722*4882a593Smuzhiyun 	struct nouveau_hwmon *hwmon;
723*4882a593Smuzhiyun 	struct device *hwmon_dev;
724*4882a593Smuzhiyun 	int ret = 0;
725*4882a593Smuzhiyun 	int i = 0;
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	if (!iccsense && !therm && !volt) {
728*4882a593Smuzhiyun 		NV_DEBUG(drm, "Skipping hwmon registration\n");
729*4882a593Smuzhiyun 		return 0;
730*4882a593Smuzhiyun 	}
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	hwmon = drm->hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL);
733*4882a593Smuzhiyun 	if (!hwmon)
734*4882a593Smuzhiyun 		return -ENOMEM;
735*4882a593Smuzhiyun 	hwmon->dev = dev;
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	if (therm && therm->attr_get && therm->attr_set) {
738*4882a593Smuzhiyun 		if (nvkm_therm_temp_get(therm) >= 0)
739*4882a593Smuzhiyun 			special_groups[i++] = &temp1_auto_point_sensor_group;
740*4882a593Smuzhiyun 		if (therm->fan_get && therm->fan_get(therm) >= 0)
741*4882a593Smuzhiyun 			special_groups[i++] = &pwm_fan_sensor_group;
742*4882a593Smuzhiyun 	}
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	special_groups[i] = NULL;
745*4882a593Smuzhiyun 	hwmon_dev = hwmon_device_register_with_info(dev->dev, "nouveau", dev,
746*4882a593Smuzhiyun 							&nouveau_chip_info,
747*4882a593Smuzhiyun 							special_groups);
748*4882a593Smuzhiyun 	if (IS_ERR(hwmon_dev)) {
749*4882a593Smuzhiyun 		ret = PTR_ERR(hwmon_dev);
750*4882a593Smuzhiyun 		NV_ERROR(drm, "Unable to register hwmon device: %d\n", ret);
751*4882a593Smuzhiyun 		return ret;
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	hwmon->hwmon = hwmon_dev;
755*4882a593Smuzhiyun 	return 0;
756*4882a593Smuzhiyun #else
757*4882a593Smuzhiyun 	return 0;
758*4882a593Smuzhiyun #endif
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun void
nouveau_hwmon_fini(struct drm_device * dev)762*4882a593Smuzhiyun nouveau_hwmon_fini(struct drm_device *dev)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
765*4882a593Smuzhiyun 	struct nouveau_hwmon *hwmon = nouveau_hwmon(dev);
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	if (!hwmon)
768*4882a593Smuzhiyun 		return;
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	if (hwmon->hwmon)
771*4882a593Smuzhiyun 		hwmon_device_unregister(hwmon->hwmon);
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	nouveau_drm(dev)->hwmon = NULL;
774*4882a593Smuzhiyun 	kfree(hwmon);
775*4882a593Smuzhiyun #endif
776*4882a593Smuzhiyun }
777