1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2007 Ben Skeggs.
3*4882a593Smuzhiyun * All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining
6*4882a593Smuzhiyun * a copy of this software and associated documentation files (the
7*4882a593Smuzhiyun * "Software"), to deal in the Software without restriction, including
8*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish,
9*4882a593Smuzhiyun * distribute, sublicense, and/or sell copies of the Software, and to
10*4882a593Smuzhiyun * permit persons to whom the Software is furnished to do so, subject to
11*4882a593Smuzhiyun * the following conditions:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the
14*4882a593Smuzhiyun * next paragraph) shall be included in all copies or substantial
15*4882a593Smuzhiyun * portions of the Software.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20*4882a593Smuzhiyun * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21*4882a593Smuzhiyun * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22*4882a593Smuzhiyun * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23*4882a593Smuzhiyun * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #ifndef __NOUVEAU_DMA_H__
28*4882a593Smuzhiyun #define __NOUVEAU_DMA_H__
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "nouveau_bo.h"
31*4882a593Smuzhiyun #include "nouveau_chan.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
34*4882a593Smuzhiyun void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * There's a hw race condition where you can't jump to your PUT offset,
38*4882a593Smuzhiyun * to avoid this we jump to offset + SKIPS and fill the difference with
39*4882a593Smuzhiyun * NOPs.
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
42*4882a593Smuzhiyun * a SKIPS value of 8. Lets assume that the race condition is to do
43*4882a593Smuzhiyun * with writing into the fetch area, we configure a fetch size of 128
44*4882a593Smuzhiyun * bytes so we need a larger SKIPS value.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun #define NOUVEAU_DMA_SKIPS (128 / 4)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Object handles - for stuff that's doesn't use handle == oclass. */
49*4882a593Smuzhiyun enum {
50*4882a593Smuzhiyun NvDmaFB = 0x80000002,
51*4882a593Smuzhiyun NvDmaTT = 0x80000003,
52*4882a593Smuzhiyun NvNotify0 = 0x80000006,
53*4882a593Smuzhiyun NvSema = 0x8000000f,
54*4882a593Smuzhiyun NvEvoSema0 = 0x80000010,
55*4882a593Smuzhiyun NvEvoSema1 = 0x80000011,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static __must_check inline int
RING_SPACE(struct nouveau_channel * chan,int size)59*4882a593Smuzhiyun RING_SPACE(struct nouveau_channel *chan, int size)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun int ret;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun ret = nouveau_dma_wait(chan, 1, size);
64*4882a593Smuzhiyun if (ret)
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun chan->dma.free -= size;
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static inline void
OUT_RING(struct nouveau_channel * chan,int data)72*4882a593Smuzhiyun OUT_RING(struct nouveau_channel *chan, int data)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define WRITE_PUT(val) do { \
78*4882a593Smuzhiyun mb(); \
79*4882a593Smuzhiyun nouveau_bo_rd32(chan->push.buffer, 0); \
80*4882a593Smuzhiyun nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
81*4882a593Smuzhiyun } while (0)
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static inline void
FIRE_RING(struct nouveau_channel * chan)84*4882a593Smuzhiyun FIRE_RING(struct nouveau_channel *chan)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun if (chan->dma.cur == chan->dma.put)
87*4882a593Smuzhiyun return;
88*4882a593Smuzhiyun chan->accel_done = true;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (chan->dma.ib_max) {
91*4882a593Smuzhiyun nv50_dma_push(chan, chan->push.addr + (chan->dma.put << 2),
92*4882a593Smuzhiyun (chan->dma.cur - chan->dma.put) << 2);
93*4882a593Smuzhiyun } else {
94*4882a593Smuzhiyun WRITE_PUT(chan->dma.cur);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun chan->dma.put = chan->dma.cur;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static inline void
WIND_RING(struct nouveau_channel * chan)101*4882a593Smuzhiyun WIND_RING(struct nouveau_channel *chan)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun chan->dma.cur = chan->dma.put;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* NV_SW object class */
107*4882a593Smuzhiyun #define NV_SW_DMA_VBLSEM 0x0000018c
108*4882a593Smuzhiyun #define NV_SW_VBLSEM_OFFSET 0x00000400
109*4882a593Smuzhiyun #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
110*4882a593Smuzhiyun #define NV_SW_VBLSEM_RELEASE 0x00000408
111*4882a593Smuzhiyun #define NV_SW_PAGE_FLIP 0x00000500
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #endif
114