xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nouveau_bo5039.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2007 Dave Airlied
3*4882a593Smuzhiyun  * All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
13*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
14*4882a593Smuzhiyun  * Software.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19*4882a593Smuzhiyun  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun  * Authors: Dave Airlied <airlied@linux.ie>
26*4882a593Smuzhiyun  *	    Ben Skeggs   <darktama@iinet.net.au>
27*4882a593Smuzhiyun  *	    Jeremy Kolb  <jkolb@brandeis.edu>
28*4882a593Smuzhiyun  */
29*4882a593Smuzhiyun #include "nouveau_bo.h"
30*4882a593Smuzhiyun #include "nouveau_dma.h"
31*4882a593Smuzhiyun #include "nouveau_drv.h"
32*4882a593Smuzhiyun #include "nouveau_mem.h"
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include <nvif/push206e.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include <nvhw/class/cl5039.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun int
nv50_bo_move_m2mf(struct nouveau_channel * chan,struct ttm_buffer_object * bo,struct ttm_resource * old_reg,struct ttm_resource * new_reg)39*4882a593Smuzhiyun nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
40*4882a593Smuzhiyun 		  struct ttm_resource *old_reg, struct ttm_resource *new_reg)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	struct nouveau_mem *mem = nouveau_mem(old_reg);
43*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
44*4882a593Smuzhiyun 	u64 length = (new_reg->num_pages << PAGE_SHIFT);
45*4882a593Smuzhiyun 	u64 src_offset = mem->vma[0].addr;
46*4882a593Smuzhiyun 	u64 dst_offset = mem->vma[1].addr;
47*4882a593Smuzhiyun 	int src_tiled = !!mem->kind;
48*4882a593Smuzhiyun 	int dst_tiled = !!nouveau_mem(new_reg)->kind;
49*4882a593Smuzhiyun 	int ret;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	while (length) {
52*4882a593Smuzhiyun 		u32 amount, stride, height;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 		ret = PUSH_WAIT(push, 18 + 6 * (src_tiled + dst_tiled));
55*4882a593Smuzhiyun 		if (ret)
56*4882a593Smuzhiyun 			return ret;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 		amount  = min(length, (u64)(4 * 1024 * 1024));
59*4882a593Smuzhiyun 		stride  = 16 * 4;
60*4882a593Smuzhiyun 		height  = amount / stride;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 		if (src_tiled) {
63*4882a593Smuzhiyun 			PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
64*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR),
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 						SET_SRC_BLOCK_SIZE,
67*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) |
68*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) |
69*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB),
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 						SET_SRC_WIDTH, stride,
72*4882a593Smuzhiyun 						SET_SRC_HEIGHT, height,
73*4882a593Smuzhiyun 						SET_SRC_DEPTH, 1,
74*4882a593Smuzhiyun 						SET_SRC_LAYER, 0,
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 						SET_SRC_ORIGIN,
77*4882a593Smuzhiyun 				  NVVAL(NV5039, SET_SRC_ORIGIN, X, 0) |
78*4882a593Smuzhiyun 				  NVVAL(NV5039, SET_SRC_ORIGIN, Y, 0));
79*4882a593Smuzhiyun 		} else {
80*4882a593Smuzhiyun 			PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
81*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH));
82*4882a593Smuzhiyun 		}
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 		if (dst_tiled) {
85*4882a593Smuzhiyun 			PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
86*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR),
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 						SET_DST_BLOCK_SIZE,
89*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) |
90*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) |
91*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB),
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 						SET_DST_WIDTH, stride,
94*4882a593Smuzhiyun 						SET_DST_HEIGHT, height,
95*4882a593Smuzhiyun 						SET_DST_DEPTH, 1,
96*4882a593Smuzhiyun 						SET_DST_LAYER, 0,
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 						SET_DST_ORIGIN,
99*4882a593Smuzhiyun 				  NVVAL(NV5039, SET_DST_ORIGIN, X, 0) |
100*4882a593Smuzhiyun 				  NVVAL(NV5039, SET_DST_ORIGIN, Y, 0));
101*4882a593Smuzhiyun 		} else {
102*4882a593Smuzhiyun 			PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
103*4882a593Smuzhiyun 				  NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH));
104*4882a593Smuzhiyun 		}
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 		PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
107*4882a593Smuzhiyun 			  NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)),
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 					OFFSET_OUT_UPPER,
110*4882a593Smuzhiyun 			  NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)));
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 		PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
113*4882a593Smuzhiyun 					OFFSET_OUT, lower_32_bits(dst_offset),
114*4882a593Smuzhiyun 					PITCH_IN, stride,
115*4882a593Smuzhiyun 					PITCH_OUT, stride,
116*4882a593Smuzhiyun 					LINE_LENGTH_IN, stride,
117*4882a593Smuzhiyun 					LINE_COUNT, height,
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 					FORMAT,
120*4882a593Smuzhiyun 			  NVDEF(NV5039, FORMAT, IN, ONE) |
121*4882a593Smuzhiyun 			  NVDEF(NV5039, FORMAT, OUT, ONE),
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 					BUFFER_NOTIFY,
124*4882a593Smuzhiyun 			  NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY));
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 		PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 		length -= amount;
129*4882a593Smuzhiyun 		src_offset += amount;
130*4882a593Smuzhiyun 		dst_offset += amount;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun int
nv50_bo_move_init(struct nouveau_channel * chan,u32 handle)137*4882a593Smuzhiyun nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
140*4882a593Smuzhiyun 	int ret;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	ret = PUSH_WAIT(push, 6);
143*4882a593Smuzhiyun 	if (ret)
144*4882a593Smuzhiyun 		return ret;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
147*4882a593Smuzhiyun 	PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle,
148*4882a593Smuzhiyun 				SET_CONTEXT_DMA_BUFFER_IN, chan->vram.handle,
149*4882a593Smuzhiyun 				SET_CONTEXT_DMA_BUFFER_OUT, chan->vram.handle);
150*4882a593Smuzhiyun 	return 0;
151*4882a593Smuzhiyun }
152