1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun #ifndef __NOUVEAU_ABI16_H__ 3*4882a593Smuzhiyun #define __NOUVEAU_ABI16_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define ABI16_IOCTL_ARGS \ 6*4882a593Smuzhiyun struct drm_device *dev, void *data, struct drm_file *file_priv 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS); 9*4882a593Smuzhiyun int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS); 10*4882a593Smuzhiyun int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS); 11*4882a593Smuzhiyun int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS); 12*4882a593Smuzhiyun int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS); 13*4882a593Smuzhiyun int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct nouveau_abi16_ntfy { 16*4882a593Smuzhiyun struct nvif_object object; 17*4882a593Smuzhiyun struct list_head head; 18*4882a593Smuzhiyun struct nvkm_mm_node *node; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct nouveau_abi16_chan { 22*4882a593Smuzhiyun struct list_head head; 23*4882a593Smuzhiyun struct nouveau_channel *chan; 24*4882a593Smuzhiyun struct list_head notifiers; 25*4882a593Smuzhiyun struct nouveau_bo *ntfy; 26*4882a593Smuzhiyun struct nouveau_vma *ntfy_vma; 27*4882a593Smuzhiyun struct nvkm_mm heap; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct nouveau_abi16 { 31*4882a593Smuzhiyun struct nvif_device device; 32*4882a593Smuzhiyun struct list_head channels; 33*4882a593Smuzhiyun u64 handles; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *); 37*4882a593Smuzhiyun int nouveau_abi16_put(struct nouveau_abi16 *, int); 38*4882a593Smuzhiyun void nouveau_abi16_fini(struct nouveau_abi16 *); 39*4882a593Smuzhiyun s32 nouveau_abi16_swclass(struct nouveau_drm *); 40*4882a593Smuzhiyun int nouveau_abi16_usif(struct drm_file *, void *data, u32 size); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 43*4882a593Smuzhiyun #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct drm_nouveau_channel_alloc { 46*4882a593Smuzhiyun uint32_t fb_ctxdma_handle; 47*4882a593Smuzhiyun uint32_t tt_ctxdma_handle; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun int channel; 50*4882a593Smuzhiyun uint32_t pushbuf_domains; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Notifier memory */ 53*4882a593Smuzhiyun uint32_t notifier_handle; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* DRM-enforced subchannel assignments */ 56*4882a593Smuzhiyun struct { 57*4882a593Smuzhiyun uint32_t handle; 58*4882a593Smuzhiyun uint32_t grclass; 59*4882a593Smuzhiyun } subchan[8]; 60*4882a593Smuzhiyun uint32_t nr_subchan; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct drm_nouveau_channel_free { 64*4882a593Smuzhiyun int channel; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct drm_nouveau_grobj_alloc { 68*4882a593Smuzhiyun int channel; 69*4882a593Smuzhiyun uint32_t handle; 70*4882a593Smuzhiyun int class; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct drm_nouveau_notifierobj_alloc { 74*4882a593Smuzhiyun uint32_t channel; 75*4882a593Smuzhiyun uint32_t handle; 76*4882a593Smuzhiyun uint32_t size; 77*4882a593Smuzhiyun uint32_t offset; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct drm_nouveau_gpuobj_free { 81*4882a593Smuzhiyun int channel; 82*4882a593Smuzhiyun uint32_t handle; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_PCI_VENDOR 3 86*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_PCI_DEVICE 4 87*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_BUS_TYPE 5 88*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_FB_SIZE 8 89*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_AGP_SIZE 9 90*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_CHIPSET_ID 11 91*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 92*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 93*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_PTIMER_TIME 14 94*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 95*4882a593Smuzhiyun #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 96*4882a593Smuzhiyun struct drm_nouveau_getparam { 97*4882a593Smuzhiyun uint64_t param; 98*4882a593Smuzhiyun uint64_t value; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct drm_nouveau_setparam { 102*4882a593Smuzhiyun uint64_t param; 103*4882a593Smuzhiyun uint64_t value; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 107*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam) 108*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 109*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 110*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc) 111*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc) 112*4882a593Smuzhiyun #define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif 115