1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun #ifndef __NVIF_CLASS_H__ 3*4882a593Smuzhiyun #define __NVIF_CLASS_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* these class numbers are made up by us, and not nvidia-assigned */ 6*4882a593Smuzhiyun #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002 11*4882a593Smuzhiyun #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 14*4882a593Smuzhiyun #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 15*4882a593Smuzhiyun #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 16*4882a593Smuzhiyun #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008 19*4882a593Smuzhiyun #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009 20*4882a593Smuzhiyun #define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009 21*4882a593Smuzhiyun #define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a 24*4882a593Smuzhiyun #define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b 25*4882a593Smuzhiyun #define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b 26*4882a593Smuzhiyun #define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c 29*4882a593Smuzhiyun #define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d 30*4882a593Smuzhiyun #define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d 31*4882a593Smuzhiyun #define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d 32*4882a593Smuzhiyun #define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d 33*4882a593Smuzhiyun #define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 36*4882a593Smuzhiyun #define NV_NULL_CLASS 0x00000030 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define NV_DEVICE /* cl0080.h */ 0x00000080 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 41*4882a593Smuzhiyun #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 42*4882a593Smuzhiyun #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define NV50_TWOD 0x0000502d 45*4882a593Smuzhiyun #define FERMI_TWOD_A 0x0000902d 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 48*4882a593Smuzhiyun #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 51*4882a593Smuzhiyun #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define NV04_DISP /* cl0046.h */ 0x00000046 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define VOLTA_USERMODE_A 0x0000c361 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069 58*4882a593Smuzhiyun #define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b 61*4882a593Smuzhiyun #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e 62*4882a593Smuzhiyun #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e 63*4882a593Smuzhiyun #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e 64*4882a593Smuzhiyun #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e 65*4882a593Smuzhiyun #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f 68*4882a593Smuzhiyun #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f 69*4882a593Smuzhiyun #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f 70*4882a593Smuzhiyun #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f 71*4882a593Smuzhiyun #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f 72*4882a593Smuzhiyun #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f 73*4882a593Smuzhiyun #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f 74*4882a593Smuzhiyun #define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f 75*4882a593Smuzhiyun #define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define NV50_DISP /* cl5070.h */ 0x00005070 78*4882a593Smuzhiyun #define G82_DISP /* cl5070.h */ 0x00008270 79*4882a593Smuzhiyun #define GT200_DISP /* cl5070.h */ 0x00008370 80*4882a593Smuzhiyun #define GT214_DISP /* cl5070.h */ 0x00008570 81*4882a593Smuzhiyun #define GT206_DISP /* cl5070.h */ 0x00008870 82*4882a593Smuzhiyun #define GF110_DISP /* cl5070.h */ 0x00009070 83*4882a593Smuzhiyun #define GK104_DISP /* cl5070.h */ 0x00009170 84*4882a593Smuzhiyun #define GK110_DISP /* cl5070.h */ 0x00009270 85*4882a593Smuzhiyun #define GM107_DISP /* cl5070.h */ 0x00009470 86*4882a593Smuzhiyun #define GM200_DISP /* cl5070.h */ 0x00009570 87*4882a593Smuzhiyun #define GP100_DISP /* cl5070.h */ 0x00009770 88*4882a593Smuzhiyun #define GP102_DISP /* cl5070.h */ 0x00009870 89*4882a593Smuzhiyun #define GV100_DISP /* cl5070.h */ 0x0000c370 90*4882a593Smuzhiyun #define TU102_DISP /* cl5070.h */ 0x0000c570 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define GV100_DISP_CAPS 0x0000c373 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define NV31_MPEG 0x00003174 95*4882a593Smuzhiyun #define G82_MPEG 0x00008274 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define NV74_VP2 0x00007476 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a 100*4882a593Smuzhiyun #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a 101*4882a593Smuzhiyun #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a 102*4882a593Smuzhiyun #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a 103*4882a593Smuzhiyun #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a 104*4882a593Smuzhiyun #define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a 105*4882a593Smuzhiyun #define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b 108*4882a593Smuzhiyun #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b 109*4882a593Smuzhiyun #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b 110*4882a593Smuzhiyun #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b 111*4882a593Smuzhiyun #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b 114*4882a593Smuzhiyun #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c 117*4882a593Smuzhiyun #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c 118*4882a593Smuzhiyun #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c 119*4882a593Smuzhiyun #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c 120*4882a593Smuzhiyun #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c 121*4882a593Smuzhiyun #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c 122*4882a593Smuzhiyun #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d 125*4882a593Smuzhiyun #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d 126*4882a593Smuzhiyun #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d 127*4882a593Smuzhiyun #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d 128*4882a593Smuzhiyun #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d 129*4882a593Smuzhiyun #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d 130*4882a593Smuzhiyun #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d 131*4882a593Smuzhiyun #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d 132*4882a593Smuzhiyun #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d 133*4882a593Smuzhiyun #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d 134*4882a593Smuzhiyun #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d 135*4882a593Smuzhiyun #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d 136*4882a593Smuzhiyun #define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d 137*4882a593Smuzhiyun #define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e 140*4882a593Smuzhiyun #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e 141*4882a593Smuzhiyun #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e 142*4882a593Smuzhiyun #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e 143*4882a593Smuzhiyun #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e 144*4882a593Smuzhiyun #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e 147*4882a593Smuzhiyun #define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define NV50_TESLA 0x00005097 150*4882a593Smuzhiyun #define G82_TESLA 0x00008297 151*4882a593Smuzhiyun #define GT200_TESLA 0x00008397 152*4882a593Smuzhiyun #define GT214_TESLA 0x00008597 153*4882a593Smuzhiyun #define GT21A_TESLA 0x00008697 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define FERMI_A /* cl9097.h */ 0x00009097 156*4882a593Smuzhiyun #define FERMI_B /* cl9097.h */ 0x00009197 157*4882a593Smuzhiyun #define FERMI_C /* cl9097.h */ 0x00009297 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define KEPLER_A /* cl9097.h */ 0x0000a097 160*4882a593Smuzhiyun #define KEPLER_B /* cl9097.h */ 0x0000a197 161*4882a593Smuzhiyun #define KEPLER_C /* cl9097.h */ 0x0000a297 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define MAXWELL_A /* cl9097.h */ 0x0000b097 164*4882a593Smuzhiyun #define MAXWELL_B /* cl9097.h */ 0x0000b197 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define PASCAL_A /* cl9097.h */ 0x0000c097 167*4882a593Smuzhiyun #define PASCAL_B /* cl9097.h */ 0x0000c197 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define VOLTA_A /* cl9097.h */ 0x0000c397 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define TURING_A /* cl9097.h */ 0x0000c597 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define NV74_BSP 0x000074b0 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define GT212_MSVLD 0x000085b1 176*4882a593Smuzhiyun #define IGT21A_MSVLD 0x000086b1 177*4882a593Smuzhiyun #define G98_MSVLD 0x000088b1 178*4882a593Smuzhiyun #define GF100_MSVLD 0x000090b1 179*4882a593Smuzhiyun #define GK104_MSVLD 0x000095b1 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define GT212_MSPDEC 0x000085b2 182*4882a593Smuzhiyun #define G98_MSPDEC 0x000088b2 183*4882a593Smuzhiyun #define GF100_MSPDEC 0x000090b2 184*4882a593Smuzhiyun #define GK104_MSPDEC 0x000095b2 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define GT212_MSPPP 0x000085b3 187*4882a593Smuzhiyun #define G98_MSPPP 0x000088b3 188*4882a593Smuzhiyun #define GF100_MSPPP 0x000090b3 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define G98_SEC 0x000088b4 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define GT212_DMA 0x000085b5 193*4882a593Smuzhiyun #define FERMI_DMA 0x000090b5 194*4882a593Smuzhiyun #define KEPLER_DMA_COPY_A 0x0000a0b5 195*4882a593Smuzhiyun #define MAXWELL_DMA_COPY_A 0x0000b0b5 196*4882a593Smuzhiyun #define PASCAL_DMA_COPY_A 0x0000c0b5 197*4882a593Smuzhiyun #define PASCAL_DMA_COPY_B 0x0000c1b5 198*4882a593Smuzhiyun #define VOLTA_DMA_COPY_A 0x0000c3b5 199*4882a593Smuzhiyun #define TURING_DMA_COPY_A 0x0000c5b5 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define FERMI_DECOMPRESS 0x000090b8 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define NV50_COMPUTE 0x000050c0 204*4882a593Smuzhiyun #define GT214_COMPUTE 0x000085c0 205*4882a593Smuzhiyun #define FERMI_COMPUTE_A 0x000090c0 206*4882a593Smuzhiyun #define FERMI_COMPUTE_B 0x000091c0 207*4882a593Smuzhiyun #define KEPLER_COMPUTE_A 0x0000a0c0 208*4882a593Smuzhiyun #define KEPLER_COMPUTE_B 0x0000a1c0 209*4882a593Smuzhiyun #define MAXWELL_COMPUTE_A 0x0000b0c0 210*4882a593Smuzhiyun #define MAXWELL_COMPUTE_B 0x0000b1c0 211*4882a593Smuzhiyun #define PASCAL_COMPUTE_A 0x0000c0c0 212*4882a593Smuzhiyun #define PASCAL_COMPUTE_B 0x0000c1c0 213*4882a593Smuzhiyun #define VOLTA_COMPUTE_A 0x0000c3c0 214*4882a593Smuzhiyun #define TURING_COMPUTE_A 0x0000c5c0 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define NV74_CIPHER 0x000074c1 217*4882a593Smuzhiyun #endif 218