1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun #ifndef __NVIF_CL5070_H__ 3*4882a593Smuzhiyun #define __NVIF_CL5070_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define NV50_DISP_MTHD 0x00 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct nv50_disp_mthd_v0 { 8*4882a593Smuzhiyun __u8 version; 9*4882a593Smuzhiyun #define NV50_DISP_SCANOUTPOS 0x00 10*4882a593Smuzhiyun __u8 method; 11*4882a593Smuzhiyun __u8 head; 12*4882a593Smuzhiyun __u8 pad03[5]; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct nv50_disp_scanoutpos_v0 { 16*4882a593Smuzhiyun __u8 version; 17*4882a593Smuzhiyun __u8 pad01[7]; 18*4882a593Smuzhiyun __s64 time[2]; 19*4882a593Smuzhiyun __u16 vblanks; 20*4882a593Smuzhiyun __u16 vblanke; 21*4882a593Smuzhiyun __u16 vtotal; 22*4882a593Smuzhiyun __u16 vline; 23*4882a593Smuzhiyun __u16 hblanks; 24*4882a593Smuzhiyun __u16 hblanke; 25*4882a593Smuzhiyun __u16 htotal; 26*4882a593Smuzhiyun __u16 hline; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct nv50_disp_mthd_v1 { 30*4882a593Smuzhiyun __u8 version; 31*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_ACQUIRE 0x01 32*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_RELEASE 0x02 33*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 34*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 35*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 36*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 37*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK 0x25 38*4882a593Smuzhiyun #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI 0x26 39*4882a593Smuzhiyun __u8 method; 40*4882a593Smuzhiyun __u16 hasht; 41*4882a593Smuzhiyun __u16 hashm; 42*4882a593Smuzhiyun __u8 pad06[2]; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct nv50_disp_acquire_v0 { 46*4882a593Smuzhiyun __u8 version; 47*4882a593Smuzhiyun __u8 or; 48*4882a593Smuzhiyun __u8 link; 49*4882a593Smuzhiyun __u8 hda; 50*4882a593Smuzhiyun __u8 pad04[4]; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct nv50_disp_dac_load_v0 { 54*4882a593Smuzhiyun __u8 version; 55*4882a593Smuzhiyun __u8 load; 56*4882a593Smuzhiyun __u8 pad02[2]; 57*4882a593Smuzhiyun __u32 data; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct nv50_disp_sor_hda_eld_v0 { 61*4882a593Smuzhiyun __u8 version; 62*4882a593Smuzhiyun __u8 pad01[7]; 63*4882a593Smuzhiyun __u8 data[]; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct nv50_disp_sor_hdmi_pwr_v0 { 67*4882a593Smuzhiyun __u8 version; 68*4882a593Smuzhiyun __u8 state; 69*4882a593Smuzhiyun __u8 max_ac_packet; 70*4882a593Smuzhiyun __u8 rekey; 71*4882a593Smuzhiyun __u8 avi_infoframe_length; 72*4882a593Smuzhiyun __u8 vendor_infoframe_length; 73*4882a593Smuzhiyun #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0) 74*4882a593Smuzhiyun #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1) 75*4882a593Smuzhiyun __u8 scdc; 76*4882a593Smuzhiyun __u8 pad07[1]; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct nv50_disp_sor_lvds_script_v0 { 80*4882a593Smuzhiyun __u8 version; 81*4882a593Smuzhiyun __u8 pad01[1]; 82*4882a593Smuzhiyun __u16 script; 83*4882a593Smuzhiyun __u8 pad04[4]; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct nv50_disp_sor_dp_mst_link_v0 { 87*4882a593Smuzhiyun __u8 version; 88*4882a593Smuzhiyun __u8 state; 89*4882a593Smuzhiyun __u8 pad02[6]; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct nv50_disp_sor_dp_mst_vcpi_v0 { 93*4882a593Smuzhiyun __u8 version; 94*4882a593Smuzhiyun __u8 pad01[1]; 95*4882a593Smuzhiyun __u8 start_slot; 96*4882a593Smuzhiyun __u8 num_slots; 97*4882a593Smuzhiyun __u16 pbn; 98*4882a593Smuzhiyun __u16 aligned_pbn; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun #endif 101