1*4882a593Smuzhiyun #ifndef __NVFW_PMU_H__ 2*4882a593Smuzhiyun #define __NVFW_PMU_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun struct nv_pmu_args { 5*4882a593Smuzhiyun u32 reserved; 6*4882a593Smuzhiyun u32 freq_hz; 7*4882a593Smuzhiyun u32 trace_size; 8*4882a593Smuzhiyun u32 trace_dma_base; 9*4882a593Smuzhiyun u16 trace_dma_base1; 10*4882a593Smuzhiyun u8 trace_dma_offset; 11*4882a593Smuzhiyun u32 trace_dma_idx; 12*4882a593Smuzhiyun bool secure_mode; 13*4882a593Smuzhiyun bool raise_priv_sec; 14*4882a593Smuzhiyun struct { 15*4882a593Smuzhiyun u32 dma_base; 16*4882a593Smuzhiyun u16 dma_base1; 17*4882a593Smuzhiyun u8 dma_offset; 18*4882a593Smuzhiyun u16 fb_size; 19*4882a593Smuzhiyun u8 dma_idx; 20*4882a593Smuzhiyun } gc6_ctx; 21*4882a593Smuzhiyun u8 pad; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define NV_PMU_UNIT_INIT 0x07 25*4882a593Smuzhiyun #define NV_PMU_UNIT_ACR 0x0a 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct nv_pmu_init_msg { 28*4882a593Smuzhiyun struct nvfw_falcon_msg hdr; 29*4882a593Smuzhiyun #define NV_PMU_INIT_MSG_INIT 0x00 30*4882a593Smuzhiyun u8 msg_type; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u8 pad; 33*4882a593Smuzhiyun u16 os_debug_entry_point; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct { 36*4882a593Smuzhiyun u16 size; 37*4882a593Smuzhiyun u16 offset; 38*4882a593Smuzhiyun u8 index; 39*4882a593Smuzhiyun u8 pad; 40*4882a593Smuzhiyun } queue_info[5]; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u16 sw_managed_area_offset; 43*4882a593Smuzhiyun u16 sw_managed_area_size; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct nv_pmu_acr_cmd { 47*4882a593Smuzhiyun struct nvfw_falcon_cmd hdr; 48*4882a593Smuzhiyun #define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00 49*4882a593Smuzhiyun #define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON 0x01 50*4882a593Smuzhiyun #define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS 0x03 51*4882a593Smuzhiyun u8 cmd_type; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct nv_pmu_acr_msg { 55*4882a593Smuzhiyun struct nvfw_falcon_cmd hdr; 56*4882a593Smuzhiyun u8 msg_type; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct nv_pmu_acr_init_wpr_region_cmd { 60*4882a593Smuzhiyun struct nv_pmu_acr_cmd cmd; 61*4882a593Smuzhiyun u32 region_id; 62*4882a593Smuzhiyun u32 wpr_offset; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct nv_pmu_acr_init_wpr_region_msg { 66*4882a593Smuzhiyun struct nv_pmu_acr_msg msg; 67*4882a593Smuzhiyun u32 error_code; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct nv_pmu_acr_bootstrap_falcon_cmd { 71*4882a593Smuzhiyun struct nv_pmu_acr_cmd cmd; 72*4882a593Smuzhiyun #define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000 73*4882a593Smuzhiyun #define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001 74*4882a593Smuzhiyun u32 flags; 75*4882a593Smuzhiyun u32 falcon_id; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct nv_pmu_acr_bootstrap_falcon_msg { 79*4882a593Smuzhiyun struct nv_pmu_acr_msg msg; 80*4882a593Smuzhiyun u32 falcon_id; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct nv_pmu_acr_bootstrap_multiple_falcons_cmd { 84*4882a593Smuzhiyun struct nv_pmu_acr_cmd cmd; 85*4882a593Smuzhiyun #define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES 0x00000000 86*4882a593Smuzhiyun #define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_NO 0x00000001 87*4882a593Smuzhiyun u32 flags; 88*4882a593Smuzhiyun u32 falcon_mask; 89*4882a593Smuzhiyun u32 use_va_mask; 90*4882a593Smuzhiyun u32 wpr_lo; 91*4882a593Smuzhiyun u32 wpr_hi; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct nv_pmu_acr_bootstrap_multiple_falcons_msg { 95*4882a593Smuzhiyun struct nv_pmu_acr_msg msg; 96*4882a593Smuzhiyun u32 falcon_mask; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun #endif 99