1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun #ifndef __NVFW_FLCN_H__ 3*4882a593Smuzhiyun #define __NVFW_FLCN_H__ 4*4882a593Smuzhiyun #include <core/os.h> 5*4882a593Smuzhiyun struct nvkm_subdev; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct loader_config { 8*4882a593Smuzhiyun u32 dma_idx; 9*4882a593Smuzhiyun u32 code_dma_base; 10*4882a593Smuzhiyun u32 code_size_total; 11*4882a593Smuzhiyun u32 code_size_to_load; 12*4882a593Smuzhiyun u32 code_entry_point; 13*4882a593Smuzhiyun u32 data_dma_base; 14*4882a593Smuzhiyun u32 data_size; 15*4882a593Smuzhiyun u32 overlay_dma_base; 16*4882a593Smuzhiyun u32 argc; 17*4882a593Smuzhiyun u32 argv; 18*4882a593Smuzhiyun u32 code_dma_base1; 19*4882a593Smuzhiyun u32 data_dma_base1; 20*4882a593Smuzhiyun u32 overlay_dma_base1; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun void 24*4882a593Smuzhiyun loader_config_dump(struct nvkm_subdev *, const struct loader_config *); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct loader_config_v1 { 27*4882a593Smuzhiyun u32 reserved; 28*4882a593Smuzhiyun u32 dma_idx; 29*4882a593Smuzhiyun u64 code_dma_base; 30*4882a593Smuzhiyun u32 code_size_total; 31*4882a593Smuzhiyun u32 code_size_to_load; 32*4882a593Smuzhiyun u32 code_entry_point; 33*4882a593Smuzhiyun u64 data_dma_base; 34*4882a593Smuzhiyun u32 data_size; 35*4882a593Smuzhiyun u64 overlay_dma_base; 36*4882a593Smuzhiyun u32 argc; 37*4882a593Smuzhiyun u32 argv; 38*4882a593Smuzhiyun } __packed; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun void 41*4882a593Smuzhiyun loader_config_v1_dump(struct nvkm_subdev *, const struct loader_config_v1 *); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct flcn_bl_dmem_desc { 44*4882a593Smuzhiyun u32 reserved[4]; 45*4882a593Smuzhiyun u32 signature[4]; 46*4882a593Smuzhiyun u32 ctx_dma; 47*4882a593Smuzhiyun u32 code_dma_base; 48*4882a593Smuzhiyun u32 non_sec_code_off; 49*4882a593Smuzhiyun u32 non_sec_code_size; 50*4882a593Smuzhiyun u32 sec_code_off; 51*4882a593Smuzhiyun u32 sec_code_size; 52*4882a593Smuzhiyun u32 code_entry_point; 53*4882a593Smuzhiyun u32 data_dma_base; 54*4882a593Smuzhiyun u32 data_size; 55*4882a593Smuzhiyun u32 code_dma_base1; 56*4882a593Smuzhiyun u32 data_dma_base1; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun void 60*4882a593Smuzhiyun flcn_bl_dmem_desc_dump(struct nvkm_subdev *, const struct flcn_bl_dmem_desc *); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct flcn_bl_dmem_desc_v1 { 63*4882a593Smuzhiyun u32 reserved[4]; 64*4882a593Smuzhiyun u32 signature[4]; 65*4882a593Smuzhiyun u32 ctx_dma; 66*4882a593Smuzhiyun u64 code_dma_base; 67*4882a593Smuzhiyun u32 non_sec_code_off; 68*4882a593Smuzhiyun u32 non_sec_code_size; 69*4882a593Smuzhiyun u32 sec_code_off; 70*4882a593Smuzhiyun u32 sec_code_size; 71*4882a593Smuzhiyun u32 code_entry_point; 72*4882a593Smuzhiyun u64 data_dma_base; 73*4882a593Smuzhiyun u32 data_size; 74*4882a593Smuzhiyun } __packed; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun void flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *, 77*4882a593Smuzhiyun const struct flcn_bl_dmem_desc_v1 *); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct flcn_bl_dmem_desc_v2 { 80*4882a593Smuzhiyun u32 reserved[4]; 81*4882a593Smuzhiyun u32 signature[4]; 82*4882a593Smuzhiyun u32 ctx_dma; 83*4882a593Smuzhiyun u64 code_dma_base; 84*4882a593Smuzhiyun u32 non_sec_code_off; 85*4882a593Smuzhiyun u32 non_sec_code_size; 86*4882a593Smuzhiyun u32 sec_code_off; 87*4882a593Smuzhiyun u32 sec_code_size; 88*4882a593Smuzhiyun u32 code_entry_point; 89*4882a593Smuzhiyun u64 data_dma_base; 90*4882a593Smuzhiyun u32 data_size; 91*4882a593Smuzhiyun u32 argc; 92*4882a593Smuzhiyun u32 argv; 93*4882a593Smuzhiyun } __packed; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun void flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *, 96*4882a593Smuzhiyun const struct flcn_bl_dmem_desc_v2 *); 97*4882a593Smuzhiyun #endif 98