xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvfw/acr.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun #ifndef __NVFW_ACR_H__
2*4882a593Smuzhiyun #define __NVFW_ACR_H__
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun struct wpr_header {
5*4882a593Smuzhiyun #define WPR_HEADER_V0_FALCON_ID_INVALID                              0xffffffff
6*4882a593Smuzhiyun 	u32 falcon_id;
7*4882a593Smuzhiyun 	u32 lsb_offset;
8*4882a593Smuzhiyun 	u32 bootstrap_owner;
9*4882a593Smuzhiyun 	u32 lazy_bootstrap;
10*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_NONE                                             0
11*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_COPY                                             1
12*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_VALIDATION_CODE_FAILED                           2
13*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_VALIDATION_DATA_FAILED                           3
14*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_VALIDATION_DONE                                  4
15*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_VALIDATION_SKIPPED                               5
16*4882a593Smuzhiyun #define WPR_HEADER_V0_STATUS_BOOTSTRAP_READY                                  6
17*4882a593Smuzhiyun 	u32 status;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun void wpr_header_dump(struct nvkm_subdev *, const struct wpr_header *);
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct wpr_header_v1 {
23*4882a593Smuzhiyun #define WPR_HEADER_V1_FALCON_ID_INVALID                              0xffffffff
24*4882a593Smuzhiyun 	u32 falcon_id;
25*4882a593Smuzhiyun 	u32 lsb_offset;
26*4882a593Smuzhiyun 	u32 bootstrap_owner;
27*4882a593Smuzhiyun 	u32 lazy_bootstrap;
28*4882a593Smuzhiyun 	u32 bin_version;
29*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_NONE                                             0
30*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_COPY                                             1
31*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_VALIDATION_CODE_FAILED                           2
32*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_VALIDATION_DATA_FAILED                           3
33*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_VALIDATION_DONE                                  4
34*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_VALIDATION_SKIPPED                               5
35*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_BOOTSTRAP_READY                                  6
36*4882a593Smuzhiyun #define WPR_HEADER_V1_STATUS_REVOCATION_CHECK_FAILED                          7
37*4882a593Smuzhiyun 	u32 status;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun void wpr_header_v1_dump(struct nvkm_subdev *, const struct wpr_header_v1 *);
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun struct lsf_signature {
43*4882a593Smuzhiyun 	u8 prd_keys[2][16];
44*4882a593Smuzhiyun 	u8 dbg_keys[2][16];
45*4882a593Smuzhiyun 	u32 b_prd_present;
46*4882a593Smuzhiyun 	u32 b_dbg_present;
47*4882a593Smuzhiyun 	u32 falcon_id;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun struct lsf_signature_v1 {
51*4882a593Smuzhiyun 	u8 prd_keys[2][16];
52*4882a593Smuzhiyun 	u8 dbg_keys[2][16];
53*4882a593Smuzhiyun 	u32 b_prd_present;
54*4882a593Smuzhiyun 	u32 b_dbg_present;
55*4882a593Smuzhiyun 	u32 falcon_id;
56*4882a593Smuzhiyun 	u32 supports_versioning;
57*4882a593Smuzhiyun 	u32 version;
58*4882a593Smuzhiyun 	u32 depmap_count;
59*4882a593Smuzhiyun 	u8 depmap[11/*LSF_LSB_DEPMAP_SIZE*/ * 2 * 4];
60*4882a593Smuzhiyun 	u8 kdf[16];
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun struct lsb_header_tail {
64*4882a593Smuzhiyun 	u32 ucode_off;
65*4882a593Smuzhiyun 	u32 ucode_size;
66*4882a593Smuzhiyun 	u32 data_size;
67*4882a593Smuzhiyun 	u32 bl_code_size;
68*4882a593Smuzhiyun 	u32 bl_imem_off;
69*4882a593Smuzhiyun 	u32 bl_data_off;
70*4882a593Smuzhiyun 	u32 bl_data_size;
71*4882a593Smuzhiyun 	u32 app_code_off;
72*4882a593Smuzhiyun 	u32 app_code_size;
73*4882a593Smuzhiyun 	u32 app_data_off;
74*4882a593Smuzhiyun 	u32 app_data_size;
75*4882a593Smuzhiyun 	u32 flags;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun struct lsb_header {
79*4882a593Smuzhiyun 	struct lsf_signature signature;
80*4882a593Smuzhiyun 	struct lsb_header_tail tail;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun void lsb_header_dump(struct nvkm_subdev *, struct lsb_header *);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun struct lsb_header_v1 {
86*4882a593Smuzhiyun 	struct lsf_signature_v1 signature;
87*4882a593Smuzhiyun 	struct lsb_header_tail tail;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun void lsb_header_v1_dump(struct nvkm_subdev *, struct lsb_header_v1 *);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct flcn_acr_desc {
93*4882a593Smuzhiyun 	union {
94*4882a593Smuzhiyun 		u8 reserved_dmem[0x200];
95*4882a593Smuzhiyun 		u32 signatures[4];
96*4882a593Smuzhiyun 	} ucode_reserved_space;
97*4882a593Smuzhiyun 	u32 wpr_region_id;
98*4882a593Smuzhiyun 	u32 wpr_offset;
99*4882a593Smuzhiyun 	u32 mmu_mem_range;
100*4882a593Smuzhiyun 	struct {
101*4882a593Smuzhiyun 		u32 no_regions;
102*4882a593Smuzhiyun 		struct {
103*4882a593Smuzhiyun 			u32 start_addr;
104*4882a593Smuzhiyun 			u32 end_addr;
105*4882a593Smuzhiyun 			u32 region_id;
106*4882a593Smuzhiyun 			u32 read_mask;
107*4882a593Smuzhiyun 			u32 write_mask;
108*4882a593Smuzhiyun 			u32 client_mask;
109*4882a593Smuzhiyun 		} region_props[2];
110*4882a593Smuzhiyun 	} regions;
111*4882a593Smuzhiyun 	u32 ucode_blob_size;
112*4882a593Smuzhiyun 	u64 ucode_blob_base __aligned(8);
113*4882a593Smuzhiyun 	struct {
114*4882a593Smuzhiyun 		u32 vpr_enabled;
115*4882a593Smuzhiyun 		u32 vpr_start;
116*4882a593Smuzhiyun 		u32 vpr_end;
117*4882a593Smuzhiyun 		u32 hdcp_policies;
118*4882a593Smuzhiyun 	} vpr_desc;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun void flcn_acr_desc_dump(struct nvkm_subdev *, struct flcn_acr_desc *);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun struct flcn_acr_desc_v1 {
124*4882a593Smuzhiyun 	u8 reserved_dmem[0x200];
125*4882a593Smuzhiyun 	u32 signatures[4];
126*4882a593Smuzhiyun 	u32 wpr_region_id;
127*4882a593Smuzhiyun 	u32 wpr_offset;
128*4882a593Smuzhiyun 	u32 mmu_memory_range;
129*4882a593Smuzhiyun 	struct {
130*4882a593Smuzhiyun 		u32 no_regions;
131*4882a593Smuzhiyun 		struct {
132*4882a593Smuzhiyun 			u32 start_addr;
133*4882a593Smuzhiyun 			u32 end_addr;
134*4882a593Smuzhiyun 			u32 region_id;
135*4882a593Smuzhiyun 			u32 read_mask;
136*4882a593Smuzhiyun 			u32 write_mask;
137*4882a593Smuzhiyun 			u32 client_mask;
138*4882a593Smuzhiyun 			u32 shadow_mem_start_addr;
139*4882a593Smuzhiyun 		} region_props[2];
140*4882a593Smuzhiyun 	} regions;
141*4882a593Smuzhiyun 	u32 ucode_blob_size;
142*4882a593Smuzhiyun 	u64 ucode_blob_base __aligned(8);
143*4882a593Smuzhiyun 	struct {
144*4882a593Smuzhiyun 		u32 vpr_enabled;
145*4882a593Smuzhiyun 		u32 vpr_start;
146*4882a593Smuzhiyun 		u32 vpr_end;
147*4882a593Smuzhiyun 		u32 hdcp_policies;
148*4882a593Smuzhiyun 	} vpr_desc;
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun void flcn_acr_desc_v1_dump(struct nvkm_subdev *, struct flcn_acr_desc_v1 *);
152*4882a593Smuzhiyun #endif
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