1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2018 Red Hat Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #include "head.h"
23*4882a593Smuzhiyun #include "core.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "nvif/push.h"
26*4882a593Smuzhiyun #include <nvif/push507c.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <nvhw/class/cl917d.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static int
head917d_dither(struct nv50_head * head,struct nv50_head_atom * asyh)31*4882a593Smuzhiyun head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
34*4882a593Smuzhiyun const int i = head->base.index;
35*4882a593Smuzhiyun int ret;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
38*4882a593Smuzhiyun return ret;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
41*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
42*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
43*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
44*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static int
head917d_base(struct nv50_head * head,struct nv50_head_atom * asyh)49*4882a593Smuzhiyun head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
52*4882a593Smuzhiyun const int i = head->base.index;
53*4882a593Smuzhiyun u32 bounds = 0;
54*4882a593Smuzhiyun int ret;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (asyh->base.cpp) {
57*4882a593Smuzhiyun switch (asyh->base.cpp) {
58*4882a593Smuzhiyun case 8: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
59*4882a593Smuzhiyun case 4: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
60*4882a593Smuzhiyun case 2: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
61*4882a593Smuzhiyun case 1: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;
62*4882a593Smuzhiyun default:
63*4882a593Smuzhiyun WARN_ON(1);
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);
67*4882a593Smuzhiyun bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, BASE_LUT, USAGE_1025);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
71*4882a593Smuzhiyun return ret;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static int
head917d_curs_set(struct nv50_head * head,struct nv50_head_atom * asyh)78*4882a593Smuzhiyun head917d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
81*4882a593Smuzhiyun const int i = head->base.index;
82*4882a593Smuzhiyun int ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = PUSH_WAIT(push, 5);
85*4882a593Smuzhiyun if (ret)
86*4882a593Smuzhiyun return ret;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
89*4882a593Smuzhiyun NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
90*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
91*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
92*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
93*4882a593Smuzhiyun NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
94*4882a593Smuzhiyun NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun int
head917d_curs_layout(struct nv50_head * head,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)103*4882a593Smuzhiyun head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw,
104*4882a593Smuzhiyun struct nv50_head_atom *asyh)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun switch (asyw->state.fb->width) {
107*4882a593Smuzhiyun case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break;
108*4882a593Smuzhiyun case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break;
109*4882a593Smuzhiyun case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break;
110*4882a593Smuzhiyun case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break;
111*4882a593Smuzhiyun default:
112*4882a593Smuzhiyun return -EINVAL;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun const struct nv50_head_func
118*4882a593Smuzhiyun head917d = {
119*4882a593Smuzhiyun .view = head907d_view,
120*4882a593Smuzhiyun .mode = head907d_mode,
121*4882a593Smuzhiyun .olut = head907d_olut,
122*4882a593Smuzhiyun .olut_size = 1024,
123*4882a593Smuzhiyun .olut_set = head907d_olut_set,
124*4882a593Smuzhiyun .olut_clr = head907d_olut_clr,
125*4882a593Smuzhiyun .core_calc = head507d_core_calc,
126*4882a593Smuzhiyun .core_set = head907d_core_set,
127*4882a593Smuzhiyun .core_clr = head907d_core_clr,
128*4882a593Smuzhiyun .curs_layout = head917d_curs_layout,
129*4882a593Smuzhiyun .curs_format = head507d_curs_format,
130*4882a593Smuzhiyun .curs_set = head917d_curs_set,
131*4882a593Smuzhiyun .curs_clr = head907d_curs_clr,
132*4882a593Smuzhiyun .base = head917d_base,
133*4882a593Smuzhiyun .ovly = head907d_ovly,
134*4882a593Smuzhiyun .dither = head917d_dither,
135*4882a593Smuzhiyun .procamp = head907d_procamp,
136*4882a593Smuzhiyun .or = head907d_or,
137*4882a593Smuzhiyun };
138