1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2018 Red Hat Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #include "head.h"
23*4882a593Smuzhiyun #include "core.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <nvif/push507c.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <nvhw/class/cl507d.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun int
head507d_procamp(struct nv50_head * head,struct nv50_head_atom * asyh)30*4882a593Smuzhiyun head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
33*4882a593Smuzhiyun const int i = head->base.index;
34*4882a593Smuzhiyun int ret;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
37*4882a593Smuzhiyun return ret;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
40*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
41*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) |
42*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) |
43*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) |
44*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PROCAMP, TRANSITION, HARD));
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun int
head507d_dither(struct nv50_head * head,struct nv50_head_atom * asyh)49*4882a593Smuzhiyun head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
52*4882a593Smuzhiyun const int i = head->base.index;
53*4882a593Smuzhiyun int ret;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
56*4882a593Smuzhiyun return ret;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
59*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
60*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
61*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
62*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun int
head507d_ovly(struct nv50_head * head,struct nv50_head_atom * asyh)67*4882a593Smuzhiyun head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
70*4882a593Smuzhiyun const int i = head->base.index;
71*4882a593Smuzhiyun u32 bounds = 0;
72*4882a593Smuzhiyun int ret;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (asyh->ovly.cpp) {
75*4882a593Smuzhiyun switch (asyh->ovly.cpp) {
76*4882a593Smuzhiyun case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
77*4882a593Smuzhiyun case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
78*4882a593Smuzhiyun default:
79*4882a593Smuzhiyun WARN_ON(1);
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);
83*4882a593Smuzhiyun } else {
84*4882a593Smuzhiyun bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
88*4882a593Smuzhiyun return ret;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun int
head507d_base(struct nv50_head * head,struct nv50_head_atom * asyh)95*4882a593Smuzhiyun head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
98*4882a593Smuzhiyun const int i = head->base.index;
99*4882a593Smuzhiyun u32 bounds = 0;
100*4882a593Smuzhiyun int ret;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (asyh->base.cpp) {
103*4882a593Smuzhiyun switch (asyh->base.cpp) {
104*4882a593Smuzhiyun case 8: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
105*4882a593Smuzhiyun case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
106*4882a593Smuzhiyun case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
107*4882a593Smuzhiyun case 1: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;
108*4882a593Smuzhiyun default:
109*4882a593Smuzhiyun WARN_ON(1);
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static int
head507d_curs_clr(struct nv50_head * head)123*4882a593Smuzhiyun head507d_curs_clr(struct nv50_head *head)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
126*4882a593Smuzhiyun const int i = head->base.index;
127*4882a593Smuzhiyun int ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
133*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
134*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |
135*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static int
head507d_curs_set(struct nv50_head * head,struct nv50_head_atom * asyh)140*4882a593Smuzhiyun head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
143*4882a593Smuzhiyun const int i = head->base.index;
144*4882a593Smuzhiyun int ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 3)))
147*4882a593Smuzhiyun return ret;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
150*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
151*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
152*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
153*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
154*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
155*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |
156*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
159*4882a593Smuzhiyun return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun int
head507d_curs_format(struct nv50_head * head,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)163*4882a593Smuzhiyun head507d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw,
164*4882a593Smuzhiyun struct nv50_head_atom *asyh)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun switch (asyw->image.format) {
167*4882a593Smuzhiyun case 0xcf: asyh->curs.format = NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8; break;
168*4882a593Smuzhiyun default:
169*4882a593Smuzhiyun WARN_ON(1);
170*4882a593Smuzhiyun return -EINVAL;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun int
head507d_curs_layout(struct nv50_head * head,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)176*4882a593Smuzhiyun head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw,
177*4882a593Smuzhiyun struct nv50_head_atom *asyh)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun switch (asyw->image.w) {
180*4882a593Smuzhiyun case 32: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break;
181*4882a593Smuzhiyun case 64: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break;
182*4882a593Smuzhiyun default:
183*4882a593Smuzhiyun return -EINVAL;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun int
head507d_core_clr(struct nv50_head * head)189*4882a593Smuzhiyun head507d_core_clr(struct nv50_head *head)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
192*4882a593Smuzhiyun const int i = head->base.index;
193*4882a593Smuzhiyun int ret;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
196*4882a593Smuzhiyun return ret;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
199*4882a593Smuzhiyun return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun static int
head507d_core_set(struct nv50_head * head,struct nv50_head_atom * asyh)203*4882a593Smuzhiyun head507d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
206*4882a593Smuzhiyun const int i = head->base.index;
207*4882a593Smuzhiyun int ret;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 9)))
210*4882a593Smuzhiyun return ret;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
213*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8));
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
216*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_SIZE, WIDTH, asyh->core.w) |
217*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_SIZE, HEIGHT, asyh->core.h),
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun HEAD_SET_STORAGE(i),
220*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) |
221*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) |
222*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) |
223*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout),
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun HEAD_SET_PARAMS(i),
226*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) |
227*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_PARAMS, KIND, asyh->core.kind) |
228*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256),
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun HEAD_SET_CONTEXT_DMA_ISO(i),
231*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTEXT_DMA_ISO, HANDLE, asyh->core.handle));
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
234*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) |
235*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y));
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* EVO will complain with INVALID_STATE if we have an
238*4882a593Smuzhiyun * active cursor and (re)specify HeadSetContextDmaIso
239*4882a593Smuzhiyun * without also updating HeadSetOffsetCursor.
240*4882a593Smuzhiyun */
241*4882a593Smuzhiyun asyh->set.curs = asyh->curs.visible;
242*4882a593Smuzhiyun asyh->set.olut = asyh->olut.handle != 0;
243*4882a593Smuzhiyun return 0;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun void
head507d_core_calc(struct nv50_head * head,struct nv50_head_atom * asyh)247*4882a593Smuzhiyun head507d_core_calc(struct nv50_head *head, struct nv50_head_atom *asyh)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct nv50_disp *disp = nv50_disp(head->base.base.dev);
250*4882a593Smuzhiyun if ((asyh->core.visible = (asyh->base.cpp != 0))) {
251*4882a593Smuzhiyun asyh->core.x = asyh->base.x;
252*4882a593Smuzhiyun asyh->core.y = asyh->base.y;
253*4882a593Smuzhiyun asyh->core.w = asyh->base.w;
254*4882a593Smuzhiyun asyh->core.h = asyh->base.h;
255*4882a593Smuzhiyun } else
256*4882a593Smuzhiyun if ((asyh->core.visible = (asyh->ovly.cpp != 0)) ||
257*4882a593Smuzhiyun (asyh->core.visible = asyh->curs.visible)) {
258*4882a593Smuzhiyun /*XXX: We need to either find some way of having the
259*4882a593Smuzhiyun * primary base layer appear black, while still
260*4882a593Smuzhiyun * being able to display the other layers, or we
261*4882a593Smuzhiyun * need to allocate a dummy black surface here.
262*4882a593Smuzhiyun */
263*4882a593Smuzhiyun asyh->core.x = 0;
264*4882a593Smuzhiyun asyh->core.y = 0;
265*4882a593Smuzhiyun asyh->core.w = asyh->state.mode.hdisplay;
266*4882a593Smuzhiyun asyh->core.h = asyh->state.mode.vdisplay;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun asyh->core.handle = disp->core->chan.vram.handle;
269*4882a593Smuzhiyun asyh->core.offset = 0;
270*4882a593Smuzhiyun asyh->core.format = NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8;
271*4882a593Smuzhiyun asyh->core.kind = NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH;
272*4882a593Smuzhiyun asyh->core.layout = NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH;
273*4882a593Smuzhiyun asyh->core.blockh = NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB;
274*4882a593Smuzhiyun asyh->core.blocks = 0;
275*4882a593Smuzhiyun asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun static int
head507d_olut_clr(struct nv50_head * head)279*4882a593Smuzhiyun head507d_olut_clr(struct nv50_head *head)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
282*4882a593Smuzhiyun const int i = head->base.index;
283*4882a593Smuzhiyun int ret;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 2)))
286*4882a593Smuzhiyun return ret;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
289*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));
290*4882a593Smuzhiyun return 0;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static int
head507d_olut_set(struct nv50_head * head,struct nv50_head_atom * asyh)294*4882a593Smuzhiyun head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
297*4882a593Smuzhiyun const int i = head->base.index;
298*4882a593Smuzhiyun int ret;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 3)))
301*4882a593Smuzhiyun return ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
304*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
305*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
306*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun HEAD_SET_BASE_LUT_HI(i),
309*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static void
head507d_olut_load(struct drm_color_lut * in,int size,void __iomem * mem)314*4882a593Smuzhiyun head507d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun for (; size--; in++, mem += 8) {
317*4882a593Smuzhiyun writew(drm_color_lut_extract(in-> red, 11) << 3, mem + 0);
318*4882a593Smuzhiyun writew(drm_color_lut_extract(in->green, 11) << 3, mem + 2);
319*4882a593Smuzhiyun writew(drm_color_lut_extract(in-> blue, 11) << 3, mem + 4);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* INTERPOLATE modes require a "next" entry to interpolate with,
323*4882a593Smuzhiyun * so we replicate the last entry to deal with this for now.
324*4882a593Smuzhiyun */
325*4882a593Smuzhiyun writew(readw(mem - 8), mem + 0);
326*4882a593Smuzhiyun writew(readw(mem - 6), mem + 2);
327*4882a593Smuzhiyun writew(readw(mem - 4), mem + 4);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun bool
head507d_olut(struct nv50_head * head,struct nv50_head_atom * asyh,int size)331*4882a593Smuzhiyun head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun if (size != 256)
334*4882a593Smuzhiyun return false;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (asyh->base.cpp == 1)
337*4882a593Smuzhiyun asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES;
338*4882a593Smuzhiyun else
339*4882a593Smuzhiyun asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun asyh->olut.load = head507d_olut_load;
342*4882a593Smuzhiyun return true;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun int
head507d_mode(struct nv50_head * head,struct nv50_head_atom * asyh)346*4882a593Smuzhiyun head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
349*4882a593Smuzhiyun struct nv50_head_mode *m = &asyh->mode;
350*4882a593Smuzhiyun const int i = head->base.index;
351*4882a593Smuzhiyun int ret;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 13)))
354*4882a593Smuzhiyun return ret;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
357*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_PIXEL_CLOCK, FREQUENCY, m->clock) |
358*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) |
359*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, ADJ1000DIV1001, FALSE) |
360*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, NOT_DRIVER, FALSE),
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun HEAD_SET_CONTROL(i),
363*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL, STRUCTURE, m->interlace));
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
366*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |
367*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |
368*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun HEAD_SET_RASTER_SIZE(i),
371*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
372*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun HEAD_SET_RASTER_SYNC_END(i),
375*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
376*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun HEAD_SET_RASTER_BLANK_END(i),
379*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
380*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun HEAD_SET_RASTER_BLANK_START(i),
383*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
384*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun HEAD_SET_RASTER_VERT_BLANK2(i),
387*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
388*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e),
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun HEAD_SET_RASTER_VERT_BLANK_DMI(i),
391*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK_DMI, DURATION, m->v.blankus));
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
394*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |
395*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |
396*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0));
397*4882a593Smuzhiyun return 0;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun int
head507d_view(struct nv50_head * head,struct nv50_head_atom * asyh)401*4882a593Smuzhiyun head507d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
404*4882a593Smuzhiyun const int i = head->base.index;
405*4882a593Smuzhiyun int ret;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if ((ret = PUSH_WAIT(push, 7)))
408*4882a593Smuzhiyun return ret;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
411*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |
412*4882a593Smuzhiyun NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |
413*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) |
414*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0));
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
417*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
418*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
421*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
422*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH),
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i),
425*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) |
426*4882a593Smuzhiyun NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH));
427*4882a593Smuzhiyun return 0;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun const struct nv50_head_func
431*4882a593Smuzhiyun head507d = {
432*4882a593Smuzhiyun .view = head507d_view,
433*4882a593Smuzhiyun .mode = head507d_mode,
434*4882a593Smuzhiyun .olut = head507d_olut,
435*4882a593Smuzhiyun .olut_size = 256,
436*4882a593Smuzhiyun .olut_set = head507d_olut_set,
437*4882a593Smuzhiyun .olut_clr = head507d_olut_clr,
438*4882a593Smuzhiyun .core_calc = head507d_core_calc,
439*4882a593Smuzhiyun .core_set = head507d_core_set,
440*4882a593Smuzhiyun .core_clr = head507d_core_clr,
441*4882a593Smuzhiyun .curs_layout = head507d_curs_layout,
442*4882a593Smuzhiyun .curs_format = head507d_curs_format,
443*4882a593Smuzhiyun .curs_set = head507d_curs_set,
444*4882a593Smuzhiyun .curs_clr = head507d_curs_clr,
445*4882a593Smuzhiyun .base = head507d_base,
446*4882a593Smuzhiyun .ovly = head507d_ovly,
447*4882a593Smuzhiyun .dither = head507d_dither,
448*4882a593Smuzhiyun .procamp = head507d_procamp,
449*4882a593Smuzhiyun };
450