1*4882a593Smuzhiyun #ifndef __NV50_KMS_H__
2*4882a593Smuzhiyun #define __NV50_KMS_H__
3*4882a593Smuzhiyun #include <linux/workqueue.h>
4*4882a593Smuzhiyun #include <nvif/mem.h>
5*4882a593Smuzhiyun #include <nvif/push.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "nouveau_display.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun struct nv50_msto;
10*4882a593Smuzhiyun struct nouveau_encoder;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct nv50_disp {
13*4882a593Smuzhiyun struct nvif_disp *disp;
14*4882a593Smuzhiyun struct nv50_core *core;
15*4882a593Smuzhiyun struct nvif_object caps;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define NV50_DISP_SYNC(c, o) ((c) * 0x040 + (o))
18*4882a593Smuzhiyun #define NV50_DISP_CORE_NTFY NV50_DISP_SYNC(0 , 0x00)
19*4882a593Smuzhiyun #define NV50_DISP_WNDW_SEM0(c) NV50_DISP_SYNC(1 + (c), 0x00)
20*4882a593Smuzhiyun #define NV50_DISP_WNDW_SEM1(c) NV50_DISP_SYNC(1 + (c), 0x10)
21*4882a593Smuzhiyun #define NV50_DISP_WNDW_NTFY(c) NV50_DISP_SYNC(1 + (c), 0x20)
22*4882a593Smuzhiyun #define NV50_DISP_BASE_SEM0(c) NV50_DISP_WNDW_SEM0(0 + (c))
23*4882a593Smuzhiyun #define NV50_DISP_BASE_SEM1(c) NV50_DISP_WNDW_SEM1(0 + (c))
24*4882a593Smuzhiyun #define NV50_DISP_BASE_NTFY(c) NV50_DISP_WNDW_NTFY(0 + (c))
25*4882a593Smuzhiyun #define NV50_DISP_OVLY_SEM0(c) NV50_DISP_WNDW_SEM0(4 + (c))
26*4882a593Smuzhiyun #define NV50_DISP_OVLY_SEM1(c) NV50_DISP_WNDW_SEM1(4 + (c))
27*4882a593Smuzhiyun #define NV50_DISP_OVLY_NTFY(c) NV50_DISP_WNDW_NTFY(4 + (c))
28*4882a593Smuzhiyun struct nouveau_bo *sync;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct mutex mutex;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static inline struct nv50_disp *
nv50_disp(struct drm_device * dev)34*4882a593Smuzhiyun nv50_disp(struct drm_device *dev)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return nouveau_display(dev)->priv;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct nv50_disp_interlock {
40*4882a593Smuzhiyun enum nv50_disp_interlock_type {
41*4882a593Smuzhiyun NV50_DISP_INTERLOCK_CORE = 0,
42*4882a593Smuzhiyun NV50_DISP_INTERLOCK_CURS,
43*4882a593Smuzhiyun NV50_DISP_INTERLOCK_BASE,
44*4882a593Smuzhiyun NV50_DISP_INTERLOCK_OVLY,
45*4882a593Smuzhiyun NV50_DISP_INTERLOCK_WNDW,
46*4882a593Smuzhiyun NV50_DISP_INTERLOCK_WIMM,
47*4882a593Smuzhiyun NV50_DISP_INTERLOCK__SIZE
48*4882a593Smuzhiyun } type;
49*4882a593Smuzhiyun u32 data;
50*4882a593Smuzhiyun u32 wimm;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun void corec37d_ntfy_init(struct nouveau_bo *, u32);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun void head907d_olut_load(struct drm_color_lut *, int size, void __iomem *);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct nv50_chan {
58*4882a593Smuzhiyun struct nvif_object user;
59*4882a593Smuzhiyun struct nvif_device *device;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct nv50_dmac {
63*4882a593Smuzhiyun struct nv50_chan base;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct nvif_push _push;
66*4882a593Smuzhiyun struct nvif_push *push;
67*4882a593Smuzhiyun u32 *ptr;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun struct nvif_object sync;
70*4882a593Smuzhiyun struct nvif_object vram;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Protects against concurrent pushbuf access to this channel, lock is
73*4882a593Smuzhiyun * grabbed by evo_wait (if the pushbuf reservation is successful) and
74*4882a593Smuzhiyun * dropped again by evo_kick. */
75*4882a593Smuzhiyun struct mutex lock;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun u32 cur;
78*4882a593Smuzhiyun u32 put;
79*4882a593Smuzhiyun u32 max;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun struct nv50_outp_atom {
83*4882a593Smuzhiyun struct list_head head;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun struct drm_encoder *encoder;
86*4882a593Smuzhiyun bool flush_disable;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun union nv50_outp_atom_mask {
89*4882a593Smuzhiyun struct {
90*4882a593Smuzhiyun bool ctrl:1;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun u8 mask;
93*4882a593Smuzhiyun } set, clr;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun int nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
97*4882a593Smuzhiyun const s32 *oclass, u8 head, void *data, u32 size,
98*4882a593Smuzhiyun s64 syncbuf, struct nv50_dmac *dmac);
99*4882a593Smuzhiyun void nv50_dmac_destroy(struct nv50_dmac *);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * For normal encoders this just returns the encoder. For active MST encoders,
103*4882a593Smuzhiyun * this returns the real outp that's driving displays on the topology.
104*4882a593Smuzhiyun * Inactive MST encoders return NULL, since they would have no real outp to
105*4882a593Smuzhiyun * return anyway.
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun u32 *evo_wait(struct nv50_dmac *, int nr);
110*4882a593Smuzhiyun void evo_kick(u32 *, struct nv50_dmac *);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun extern const u64 disp50xx_modifiers[];
113*4882a593Smuzhiyun extern const u64 disp90xx_modifiers[];
114*4882a593Smuzhiyun extern const u64 wndwc57e_modifiers[];
115*4882a593Smuzhiyun #endif
116