xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv50/curs507a.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2018 Red Hat Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun #include "curs.h"
23*4882a593Smuzhiyun #include "core.h"
24*4882a593Smuzhiyun #include "head.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <nvif/cl507a.h>
27*4882a593Smuzhiyun #include <nvif/timer.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include <nvhw/class/cl507a.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
32*4882a593Smuzhiyun #include <drm/drm_plane_helper.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun bool
curs507a_space(struct nv50_wndw * wndw)35*4882a593Smuzhiyun curs507a_space(struct nv50_wndw *wndw)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	nvif_msec(&nouveau_drm(wndw->plane.dev)->client.device, 100,
38*4882a593Smuzhiyun 		if (NVIF_TV32(&wndw->wimm.base.user, NV507A, FREE, COUNT, >=, 4))
39*4882a593Smuzhiyun 			return true;
40*4882a593Smuzhiyun 	);
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	WARN_ON(1);
43*4882a593Smuzhiyun 	return false;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun static int
curs507a_update(struct nv50_wndw * wndw,u32 * interlock)47*4882a593Smuzhiyun curs507a_update(struct nv50_wndw *wndw, u32 *interlock)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	struct nvif_object *user = &wndw->wimm.base.user;
50*4882a593Smuzhiyun 	int ret = nvif_chan_wait(&wndw->wimm, 1);
51*4882a593Smuzhiyun 	if (ret == 0) {
52*4882a593Smuzhiyun 		NVIF_WR32(user, NV507A, UPDATE,
53*4882a593Smuzhiyun 			  NVDEF(NV507A, UPDATE, INTERLOCK_WITH_CORE, DISABLE));
54*4882a593Smuzhiyun 	}
55*4882a593Smuzhiyun 	return ret;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun static int
curs507a_point(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw)59*4882a593Smuzhiyun curs507a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct nvif_object *user = &wndw->wimm.base.user;
62*4882a593Smuzhiyun 	int ret = nvif_chan_wait(&wndw->wimm, 1);
63*4882a593Smuzhiyun 	if (ret == 0) {
64*4882a593Smuzhiyun 		NVIF_WR32(user, NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT,
65*4882a593Smuzhiyun 			  NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, X, asyw->point.x) |
66*4882a593Smuzhiyun 			  NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, Y, asyw->point.y));
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 	return ret;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun const struct nv50_wimm_func
72*4882a593Smuzhiyun curs507a = {
73*4882a593Smuzhiyun 	.point = curs507a_point,
74*4882a593Smuzhiyun 	.update = curs507a_update,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun static void
curs507a_prepare(struct nv50_wndw * wndw,struct nv50_head_atom * asyh,struct nv50_wndw_atom * asyw)78*4882a593Smuzhiyun curs507a_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
79*4882a593Smuzhiyun 		 struct nv50_wndw_atom *asyw)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	u32 handle = nv50_disp(wndw->plane.dev)->core->chan.vram.handle;
82*4882a593Smuzhiyun 	u32 offset = asyw->image.offset[0];
83*4882a593Smuzhiyun 	if (asyh->curs.handle != handle || asyh->curs.offset != offset) {
84*4882a593Smuzhiyun 		asyh->curs.handle = handle;
85*4882a593Smuzhiyun 		asyh->curs.offset = offset;
86*4882a593Smuzhiyun 		asyh->set.curs = asyh->curs.visible;
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static void
curs507a_release(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)91*4882a593Smuzhiyun curs507a_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
92*4882a593Smuzhiyun 		 struct nv50_head_atom *asyh)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	asyh->curs.visible = false;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static int
curs507a_acquire(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)98*4882a593Smuzhiyun curs507a_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
99*4882a593Smuzhiyun 		 struct nv50_head_atom *asyh)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct nv50_head *head = nv50_head(asyw->state.crtc);
102*4882a593Smuzhiyun 	int ret;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
105*4882a593Smuzhiyun 						  DRM_PLANE_HELPER_NO_SCALING,
106*4882a593Smuzhiyun 						  DRM_PLANE_HELPER_NO_SCALING,
107*4882a593Smuzhiyun 						  true, true);
108*4882a593Smuzhiyun 	asyh->curs.visible = asyw->state.visible;
109*4882a593Smuzhiyun 	if (ret || !asyh->curs.visible)
110*4882a593Smuzhiyun 		return ret;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	if (asyw->image.w != asyw->image.h)
113*4882a593Smuzhiyun 		return -EINVAL;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	ret = head->func->curs_layout(head, asyw, asyh);
116*4882a593Smuzhiyun 	if (ret)
117*4882a593Smuzhiyun 		return ret;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	return head->func->curs_format(head, asyw, asyh);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static const u32
123*4882a593Smuzhiyun curs507a_format[] = {
124*4882a593Smuzhiyun 	DRM_FORMAT_ARGB8888,
125*4882a593Smuzhiyun 	0
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static const struct nv50_wndw_func
129*4882a593Smuzhiyun curs507a_wndw = {
130*4882a593Smuzhiyun 	.acquire = curs507a_acquire,
131*4882a593Smuzhiyun 	.release = curs507a_release,
132*4882a593Smuzhiyun 	.prepare = curs507a_prepare,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun int
curs507a_new_(const struct nv50_wimm_func * func,struct nouveau_drm * drm,int head,s32 oclass,u32 interlock_data,struct nv50_wndw ** pwndw)136*4882a593Smuzhiyun curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm,
137*4882a593Smuzhiyun 	      int head, s32 oclass, u32 interlock_data,
138*4882a593Smuzhiyun 	      struct nv50_wndw **pwndw)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	struct nv50_disp_cursor_v0 args = {
141*4882a593Smuzhiyun 		.head = head,
142*4882a593Smuzhiyun 	};
143*4882a593Smuzhiyun 	struct nv50_disp *disp = nv50_disp(drm->dev);
144*4882a593Smuzhiyun 	struct nv50_wndw *wndw;
145*4882a593Smuzhiyun 	int ret;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	ret = nv50_wndw_new_(&curs507a_wndw, drm->dev, DRM_PLANE_TYPE_CURSOR,
148*4882a593Smuzhiyun 			     "curs", head, curs507a_format, BIT(head),
149*4882a593Smuzhiyun 			     NV50_DISP_INTERLOCK_CURS, interlock_data, &wndw);
150*4882a593Smuzhiyun 	if (*pwndw = wndw, ret)
151*4882a593Smuzhiyun 		return ret;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	ret = nvif_object_ctor(&disp->disp->object, "kmsCurs", 0, oclass,
154*4882a593Smuzhiyun 			       &args, sizeof(args), &wndw->wimm.base.user);
155*4882a593Smuzhiyun 	if (ret) {
156*4882a593Smuzhiyun 		NV_ERROR(drm, "curs%04x allocation failed: %d\n", oclass, ret);
157*4882a593Smuzhiyun 		return ret;
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	nvif_object_map(&wndw->wimm.base.user, NULL, 0);
161*4882a593Smuzhiyun 	wndw->immd = func;
162*4882a593Smuzhiyun 	wndw->ctxdma.parent = NULL;
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun int
curs507a_new(struct nouveau_drm * drm,int head,s32 oclass,struct nv50_wndw ** pwndw)167*4882a593Smuzhiyun curs507a_new(struct nouveau_drm *drm, int head, s32 oclass,
168*4882a593Smuzhiyun 	     struct nv50_wndw **pwndw)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	return curs507a_new_(&curs507a, drm, head, oclass,
171*4882a593Smuzhiyun 			     0x00000001 << (head * 8), pwndw);
172*4882a593Smuzhiyun }
173