xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2009 Francisco Jerez.
3*4882a593Smuzhiyun  * All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining
6*4882a593Smuzhiyun  * a copy of this software and associated documentation files (the
7*4882a593Smuzhiyun  * "Software"), to deal in the Software without restriction, including
8*4882a593Smuzhiyun  * without limitation the rights to use, copy, modify, merge, publish,
9*4882a593Smuzhiyun  * distribute, sublicense, and/or sell copies of the Software, and to
10*4882a593Smuzhiyun  * permit persons to whom the Software is furnished to do so, subject to
11*4882a593Smuzhiyun  * the following conditions:
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the
14*4882a593Smuzhiyun  * next paragraph) shall be included in all copies or substantial
15*4882a593Smuzhiyun  * portions of the Software.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20*4882a593Smuzhiyun  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21*4882a593Smuzhiyun  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22*4882a593Smuzhiyun  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23*4882a593Smuzhiyun  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #ifndef __NV17_TV_H__
28*4882a593Smuzhiyun #define __NV17_TV_H__
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct nv17_tv_state {
31*4882a593Smuzhiyun 	uint8_t tv_enc[0x40];
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	uint32_t hfilter[4][7];
34*4882a593Smuzhiyun 	uint32_t hfilter2[4][7];
35*4882a593Smuzhiyun 	uint32_t vfilter[4][7];
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	uint32_t ptv_200;
38*4882a593Smuzhiyun 	uint32_t ptv_204;
39*4882a593Smuzhiyun 	uint32_t ptv_208;
40*4882a593Smuzhiyun 	uint32_t ptv_20c;
41*4882a593Smuzhiyun 	uint32_t ptv_304;
42*4882a593Smuzhiyun 	uint32_t ptv_500;
43*4882a593Smuzhiyun 	uint32_t ptv_504;
44*4882a593Smuzhiyun 	uint32_t ptv_508;
45*4882a593Smuzhiyun 	uint32_t ptv_600;
46*4882a593Smuzhiyun 	uint32_t ptv_604;
47*4882a593Smuzhiyun 	uint32_t ptv_608;
48*4882a593Smuzhiyun 	uint32_t ptv_60c;
49*4882a593Smuzhiyun 	uint32_t ptv_610;
50*4882a593Smuzhiyun 	uint32_t ptv_614;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun enum nv17_tv_norm{
54*4882a593Smuzhiyun 	TV_NORM_PAL,
55*4882a593Smuzhiyun 	TV_NORM_PAL_M,
56*4882a593Smuzhiyun 	TV_NORM_PAL_N,
57*4882a593Smuzhiyun 	TV_NORM_PAL_NC,
58*4882a593Smuzhiyun 	TV_NORM_NTSC_M,
59*4882a593Smuzhiyun 	TV_NORM_NTSC_J,
60*4882a593Smuzhiyun 	NUM_LD_TV_NORMS,
61*4882a593Smuzhiyun 	TV_NORM_HD480I = NUM_LD_TV_NORMS,
62*4882a593Smuzhiyun 	TV_NORM_HD480P,
63*4882a593Smuzhiyun 	TV_NORM_HD576I,
64*4882a593Smuzhiyun 	TV_NORM_HD576P,
65*4882a593Smuzhiyun 	TV_NORM_HD720P,
66*4882a593Smuzhiyun 	TV_NORM_HD1080I,
67*4882a593Smuzhiyun 	NUM_TV_NORMS
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct nv17_tv_encoder {
71*4882a593Smuzhiyun 	struct nouveau_encoder base;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	struct nv17_tv_state state;
74*4882a593Smuzhiyun 	struct nv17_tv_state saved_state;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	int overscan;
77*4882a593Smuzhiyun 	int flicker;
78*4882a593Smuzhiyun 	int saturation;
79*4882a593Smuzhiyun 	int hue;
80*4882a593Smuzhiyun 	enum nv17_tv_norm tv_norm;
81*4882a593Smuzhiyun 	int subconnector;
82*4882a593Smuzhiyun 	int select_subconnector;
83*4882a593Smuzhiyun 	uint32_t pin_mask;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun #define to_tv_enc(x) container_of(nouveau_encoder(x),		\
86*4882a593Smuzhiyun 				  struct nv17_tv_encoder, base)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun extern const char * const nv17_tv_norm_names[NUM_TV_NORMS];
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun extern struct nv17_tv_norm_params {
91*4882a593Smuzhiyun 	enum {
92*4882a593Smuzhiyun 		TV_ENC_MODE,
93*4882a593Smuzhiyun 		CTV_ENC_MODE,
94*4882a593Smuzhiyun 	} kind;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	union {
97*4882a593Smuzhiyun 		struct {
98*4882a593Smuzhiyun 			int hdisplay;
99*4882a593Smuzhiyun 			int vdisplay;
100*4882a593Smuzhiyun 			int vrefresh; /* mHz */
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 			uint8_t tv_enc[0x40];
103*4882a593Smuzhiyun 		} tv_enc_mode;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 		struct {
106*4882a593Smuzhiyun 			struct drm_display_mode mode;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 			uint32_t ctv_regs[38];
109*4882a593Smuzhiyun 		} ctv_enc_mode;
110*4882a593Smuzhiyun 	};
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun } nv17_tv_norms[NUM_TV_NORMS];
113*4882a593Smuzhiyun #define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm])
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun extern const struct drm_display_mode nv17_tv_modes[];
116*4882a593Smuzhiyun 
interpolate(int y0,int y1,int y2,int x)117*4882a593Smuzhiyun static inline int interpolate(int y0, int y1, int y2, int x)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state);
123*4882a593Smuzhiyun void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state);
124*4882a593Smuzhiyun void nv17_tv_update_properties(struct drm_encoder *encoder);
125*4882a593Smuzhiyun void nv17_tv_update_rescaler(struct drm_encoder *encoder);
126*4882a593Smuzhiyun void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun /* TV hardware access functions */
129*4882a593Smuzhiyun 
nv_write_ptv(struct drm_device * dev,uint32_t reg,uint32_t val)130*4882a593Smuzhiyun static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
131*4882a593Smuzhiyun 				uint32_t val)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	struct nvif_device *device = &nouveau_drm(dev)->client.device;
134*4882a593Smuzhiyun 	nvif_wr32(&device->object, reg, val);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
nv_read_ptv(struct drm_device * dev,uint32_t reg)137*4882a593Smuzhiyun static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct nvif_device *device = &nouveau_drm(dev)->client.device;
140*4882a593Smuzhiyun 	return nvif_rd32(&device->object, reg);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
nv_write_tv_enc(struct drm_device * dev,uint8_t reg,uint8_t val)143*4882a593Smuzhiyun static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
144*4882a593Smuzhiyun 				   uint8_t val)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
147*4882a593Smuzhiyun 	nv_write_ptv(dev, NV_PTV_TV_DATA, val);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
nv_read_tv_enc(struct drm_device * dev,uint8_t reg)150*4882a593Smuzhiyun static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
153*4882a593Smuzhiyun 	return nv_read_ptv(dev, NV_PTV_TV_DATA);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #define nv_load_ptv(dev, state, reg) \
157*4882a593Smuzhiyun 	nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg)
158*4882a593Smuzhiyun #define nv_save_ptv(dev, state, reg) \
159*4882a593Smuzhiyun 	state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg)
160*4882a593Smuzhiyun #define nv_load_tv_enc(dev, state, reg) \
161*4882a593Smuzhiyun 	nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg])
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #endif
164