xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/disp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */
2*4882a593Smuzhiyun #ifndef __NV04_DISPLAY_H__
3*4882a593Smuzhiyun #define __NV04_DISPLAY_H__
4*4882a593Smuzhiyun #include <subdev/bios.h>
5*4882a593Smuzhiyun #include <subdev/bios/pll.h>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "nouveau_display.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun struct nouveau_encoder;
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun enum nv04_fp_display_regs {
12*4882a593Smuzhiyun 	FP_DISPLAY_END,
13*4882a593Smuzhiyun 	FP_TOTAL,
14*4882a593Smuzhiyun 	FP_CRTC,
15*4882a593Smuzhiyun 	FP_SYNC_START,
16*4882a593Smuzhiyun 	FP_SYNC_END,
17*4882a593Smuzhiyun 	FP_VALID_START,
18*4882a593Smuzhiyun 	FP_VALID_END
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun struct nv04_crtc_reg {
22*4882a593Smuzhiyun 	unsigned char MiscOutReg;
23*4882a593Smuzhiyun 	uint8_t CRTC[0xa0];
24*4882a593Smuzhiyun 	uint8_t CR58[0x10];
25*4882a593Smuzhiyun 	uint8_t Sequencer[5];
26*4882a593Smuzhiyun 	uint8_t Graphics[9];
27*4882a593Smuzhiyun 	uint8_t Attribute[21];
28*4882a593Smuzhiyun 	unsigned char DAC[768];
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	/* PCRTC regs */
31*4882a593Smuzhiyun 	uint32_t fb_start;
32*4882a593Smuzhiyun 	uint32_t crtc_cfg;
33*4882a593Smuzhiyun 	uint32_t cursor_cfg;
34*4882a593Smuzhiyun 	uint32_t gpio_ext;
35*4882a593Smuzhiyun 	uint32_t crtc_830;
36*4882a593Smuzhiyun 	uint32_t crtc_834;
37*4882a593Smuzhiyun 	uint32_t crtc_850;
38*4882a593Smuzhiyun 	uint32_t crtc_eng_ctrl;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	/* PRAMDAC regs */
41*4882a593Smuzhiyun 	uint32_t nv10_cursync;
42*4882a593Smuzhiyun 	struct nvkm_pll_vals pllvals;
43*4882a593Smuzhiyun 	uint32_t ramdac_gen_ctrl;
44*4882a593Smuzhiyun 	uint32_t ramdac_630;
45*4882a593Smuzhiyun 	uint32_t ramdac_634;
46*4882a593Smuzhiyun 	uint32_t tv_setup;
47*4882a593Smuzhiyun 	uint32_t tv_vtotal;
48*4882a593Smuzhiyun 	uint32_t tv_vskew;
49*4882a593Smuzhiyun 	uint32_t tv_vsync_delay;
50*4882a593Smuzhiyun 	uint32_t tv_htotal;
51*4882a593Smuzhiyun 	uint32_t tv_hskew;
52*4882a593Smuzhiyun 	uint32_t tv_hsync_delay;
53*4882a593Smuzhiyun 	uint32_t tv_hsync_delay2;
54*4882a593Smuzhiyun 	uint32_t fp_horiz_regs[7];
55*4882a593Smuzhiyun 	uint32_t fp_vert_regs[7];
56*4882a593Smuzhiyun 	uint32_t dither;
57*4882a593Smuzhiyun 	uint32_t fp_control;
58*4882a593Smuzhiyun 	uint32_t dither_regs[6];
59*4882a593Smuzhiyun 	uint32_t fp_debug_0;
60*4882a593Smuzhiyun 	uint32_t fp_debug_1;
61*4882a593Smuzhiyun 	uint32_t fp_debug_2;
62*4882a593Smuzhiyun 	uint32_t fp_margin_color;
63*4882a593Smuzhiyun 	uint32_t ramdac_8c0;
64*4882a593Smuzhiyun 	uint32_t ramdac_a20;
65*4882a593Smuzhiyun 	uint32_t ramdac_a24;
66*4882a593Smuzhiyun 	uint32_t ramdac_a34;
67*4882a593Smuzhiyun 	uint32_t ctv_regs[38];
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct nv04_output_reg {
71*4882a593Smuzhiyun 	uint32_t output;
72*4882a593Smuzhiyun 	int head;
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct nv04_mode_state {
76*4882a593Smuzhiyun 	struct nv04_crtc_reg crtc_reg[2];
77*4882a593Smuzhiyun 	uint32_t pllsel;
78*4882a593Smuzhiyun 	uint32_t sel_clk;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun struct nv04_display {
82*4882a593Smuzhiyun 	struct nv04_mode_state mode_reg;
83*4882a593Smuzhiyun 	struct nv04_mode_state saved_reg;
84*4882a593Smuzhiyun 	uint32_t saved_vga_font[4][16384];
85*4882a593Smuzhiyun 	uint32_t dac_users[4];
86*4882a593Smuzhiyun 	struct nouveau_bo *image[2];
87*4882a593Smuzhiyun 	struct nvif_notify flip;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static inline struct nv04_display *
nv04_display(struct drm_device * dev)91*4882a593Smuzhiyun nv04_display(struct drm_device *dev)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	return nouveau_display(dev)->priv;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* nv04_display.c */
97*4882a593Smuzhiyun int nv04_display_create(struct drm_device *);
98*4882a593Smuzhiyun struct nouveau_connector *
99*4882a593Smuzhiyun nv04_encoder_get_connector(struct nouveau_encoder *nv_encoder);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* nv04_crtc.c */
102*4882a593Smuzhiyun int nv04_crtc_create(struct drm_device *, int index);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* nv04_dac.c */
105*4882a593Smuzhiyun int nv04_dac_create(struct drm_connector *, struct dcb_output *);
106*4882a593Smuzhiyun uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
107*4882a593Smuzhiyun int nv04_dac_output_offset(struct drm_encoder *encoder);
108*4882a593Smuzhiyun void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
109*4882a593Smuzhiyun bool nv04_dac_in_use(struct drm_encoder *encoder);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* nv04_dfp.c */
112*4882a593Smuzhiyun int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
113*4882a593Smuzhiyun int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
114*4882a593Smuzhiyun void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
115*4882a593Smuzhiyun 			       int head, bool dl);
116*4882a593Smuzhiyun void nv04_dfp_disable(struct drm_device *dev, int head);
117*4882a593Smuzhiyun void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /* nv04_tv.c */
120*4882a593Smuzhiyun int nv04_tv_identify(struct drm_device *dev, int i2c_index);
121*4882a593Smuzhiyun int nv04_tv_create(struct drm_connector *, struct dcb_output *);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* nv17_tv.c */
124*4882a593Smuzhiyun int nv17_tv_create(struct drm_connector *, struct dcb_output *);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* overlay.c */
127*4882a593Smuzhiyun void nouveau_overlay_init(struct drm_device *dev);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static inline bool
nv_two_heads(struct drm_device * dev)130*4882a593Smuzhiyun nv_two_heads(struct drm_device *dev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
133*4882a593Smuzhiyun 	const int impl = dev->pdev->device & 0x0ff0;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
136*4882a593Smuzhiyun 	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
137*4882a593Smuzhiyun 		return true;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return false;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static inline bool
nv_gf4_disp_arch(struct drm_device * dev)143*4882a593Smuzhiyun nv_gf4_disp_arch(struct drm_device *dev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static inline bool
nv_two_reg_pll(struct drm_device * dev)149*4882a593Smuzhiyun nv_two_reg_pll(struct drm_device *dev)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
152*4882a593Smuzhiyun 	const int impl = dev->pdev->device & 0x0ff0;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
155*4882a593Smuzhiyun 		return true;
156*4882a593Smuzhiyun 	return false;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static inline bool
nv_match_device(struct drm_device * dev,unsigned device,unsigned sub_vendor,unsigned sub_device)160*4882a593Smuzhiyun nv_match_device(struct drm_device *dev, unsigned device,
161*4882a593Smuzhiyun 		unsigned sub_vendor, unsigned sub_device)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	return dev->pdev->device == device &&
164*4882a593Smuzhiyun 		dev->pdev->subsystem_vendor == sub_vendor &&
165*4882a593Smuzhiyun 		dev->pdev->subsystem_device == sub_device;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun #include <subdev/bios/init.h>
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static inline void
nouveau_bios_run_init_table(struct drm_device * dev,u16 table,struct dcb_output * outp,int crtc)171*4882a593Smuzhiyun nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
172*4882a593Smuzhiyun 			    struct dcb_output *outp, int crtc)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	nvbios_init(&nvxx_bios(&nouveau_drm(dev)->client.device)->subdev, table,
175*4882a593Smuzhiyun 		init.outp = outp;
176*4882a593Smuzhiyun 		init.head = crtc;
177*4882a593Smuzhiyun 	);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun int nv04_flip_complete(struct nvif_notify *);
181*4882a593Smuzhiyun #endif
182