1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/dma-mapping.h>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include "msm_drv.h"
7*4882a593Smuzhiyun #include "msm_mmu.h"
8*4882a593Smuzhiyun #include "adreno/adreno_gpu.h"
9*4882a593Smuzhiyun #include "adreno/a2xx.xml.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct msm_gpummu {
12*4882a593Smuzhiyun struct msm_mmu base;
13*4882a593Smuzhiyun struct msm_gpu *gpu;
14*4882a593Smuzhiyun dma_addr_t pt_base;
15*4882a593Smuzhiyun uint32_t *table;
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun #define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define GPUMMU_VA_START SZ_16M
20*4882a593Smuzhiyun #define GPUMMU_VA_RANGE (0xfff * SZ_64K)
21*4882a593Smuzhiyun #define GPUMMU_PAGE_SIZE SZ_4K
22*4882a593Smuzhiyun #define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
23*4882a593Smuzhiyun
msm_gpummu_detach(struct msm_mmu * mmu)24*4882a593Smuzhiyun static void msm_gpummu_detach(struct msm_mmu *mmu)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
msm_gpummu_map(struct msm_mmu * mmu,uint64_t iova,struct sg_table * sgt,size_t len,int prot)28*4882a593Smuzhiyun static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
29*4882a593Smuzhiyun struct sg_table *sgt, size_t len, int prot)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
32*4882a593Smuzhiyun unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
33*4882a593Smuzhiyun struct sg_dma_page_iter dma_iter;
34*4882a593Smuzhiyun unsigned prot_bits = 0;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (prot & IOMMU_WRITE)
37*4882a593Smuzhiyun prot_bits |= 1;
38*4882a593Smuzhiyun if (prot & IOMMU_READ)
39*4882a593Smuzhiyun prot_bits |= 2;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun for_each_sgtable_dma_page(sgt, &dma_iter, 0) {
42*4882a593Smuzhiyun dma_addr_t addr = sg_page_iter_dma_address(&dma_iter);
43*4882a593Smuzhiyun int i;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun for (i = 0; i < PAGE_SIZE; i += GPUMMU_PAGE_SIZE)
46*4882a593Smuzhiyun gpummu->table[idx++] = (addr + i) | prot_bits;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* we can improve by deferring flush for multiple map() */
50*4882a593Smuzhiyun gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
51*4882a593Smuzhiyun A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
52*4882a593Smuzhiyun A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
msm_gpummu_unmap(struct msm_mmu * mmu,uint64_t iova,size_t len)56*4882a593Smuzhiyun static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
59*4882a593Smuzhiyun unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
60*4882a593Smuzhiyun unsigned i;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun for (i = 0; i < len / GPUMMU_PAGE_SIZE; i++, idx++)
63*4882a593Smuzhiyun gpummu->table[idx] = 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
66*4882a593Smuzhiyun A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
67*4882a593Smuzhiyun A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
msm_gpummu_destroy(struct msm_mmu * mmu)71*4882a593Smuzhiyun static void msm_gpummu_destroy(struct msm_mmu *mmu)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
76*4882a593Smuzhiyun DMA_ATTR_FORCE_CONTIGUOUS);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun kfree(gpummu);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct msm_mmu_funcs funcs = {
82*4882a593Smuzhiyun .detach = msm_gpummu_detach,
83*4882a593Smuzhiyun .map = msm_gpummu_map,
84*4882a593Smuzhiyun .unmap = msm_gpummu_unmap,
85*4882a593Smuzhiyun .destroy = msm_gpummu_destroy,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
msm_gpummu_new(struct device * dev,struct msm_gpu * gpu)88*4882a593Smuzhiyun struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct msm_gpummu *gpummu;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
93*4882a593Smuzhiyun if (!gpummu)
94*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base,
97*4882a593Smuzhiyun GFP_KERNEL | __GFP_ZERO, DMA_ATTR_FORCE_CONTIGUOUS);
98*4882a593Smuzhiyun if (!gpummu->table) {
99*4882a593Smuzhiyun kfree(gpummu);
100*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun gpummu->gpu = gpu;
104*4882a593Smuzhiyun msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return &gpummu->base;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
msm_gpummu_params(struct msm_mmu * mmu,dma_addr_t * pt_base,dma_addr_t * tran_error)109*4882a593Smuzhiyun void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
110*4882a593Smuzhiyun dma_addr_t *tran_error)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun dma_addr_t base = to_msm_gpummu(mmu)->pt_base;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun *pt_base = base;
115*4882a593Smuzhiyun *tran_error = base + TABLE_SIZE; /* 32-byte aligned */
116*4882a593Smuzhiyun }
117