xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2013 Red Hat
4*4882a593Smuzhiyun  * Author: Rob Clark <robdclark@gmail.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "hdmi.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun struct hdmi_i2c_adapter {
10*4882a593Smuzhiyun 	struct i2c_adapter base;
11*4882a593Smuzhiyun 	struct hdmi *hdmi;
12*4882a593Smuzhiyun 	bool sw_done;
13*4882a593Smuzhiyun 	wait_queue_head_t ddc_event;
14*4882a593Smuzhiyun };
15*4882a593Smuzhiyun #define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base)
16*4882a593Smuzhiyun 
init_ddc(struct hdmi_i2c_adapter * hdmi_i2c)17*4882a593Smuzhiyun static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun 	struct hdmi *hdmi = hdmi_i2c->hdmi;
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
22*4882a593Smuzhiyun 			HDMI_DDC_CTRL_SW_STATUS_RESET);
23*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
24*4882a593Smuzhiyun 			HDMI_DDC_CTRL_SOFT_RESET);
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_SPEED,
27*4882a593Smuzhiyun 			HDMI_DDC_SPEED_THRESHOLD(2) |
28*4882a593Smuzhiyun 			HDMI_DDC_SPEED_PRESCALE(10));
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_SETUP,
31*4882a593Smuzhiyun 			HDMI_DDC_SETUP_TIMEOUT(0xff));
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	/* enable reference timer for 27us */
34*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_REF,
35*4882a593Smuzhiyun 			HDMI_DDC_REF_REFTIMER_ENABLE |
36*4882a593Smuzhiyun 			HDMI_DDC_REF_REFTIMER(27));
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
ddc_clear_irq(struct hdmi_i2c_adapter * hdmi_i2c)39*4882a593Smuzhiyun static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	struct hdmi *hdmi = hdmi_i2c->hdmi;
42*4882a593Smuzhiyun 	struct drm_device *dev = hdmi->dev;
43*4882a593Smuzhiyun 	uint32_t retry = 0xffff;
44*4882a593Smuzhiyun 	uint32_t ddc_int_ctrl;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	do {
47*4882a593Smuzhiyun 		--retry;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 		hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
50*4882a593Smuzhiyun 				HDMI_DDC_INT_CTRL_SW_DONE_ACK |
51*4882a593Smuzhiyun 				HDMI_DDC_INT_CTRL_SW_DONE_MASK);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 		ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	} while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	if (!retry) {
58*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n");
59*4882a593Smuzhiyun 		return -ETIMEDOUT;
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	hdmi_i2c->sw_done = false;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define MAX_TRANSACTIONS 4
68*4882a593Smuzhiyun 
sw_done(struct hdmi_i2c_adapter * hdmi_i2c)69*4882a593Smuzhiyun static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct hdmi *hdmi = hdmi_i2c->hdmi;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (!hdmi_i2c->sw_done) {
74*4882a593Smuzhiyun 		uint32_t ddc_int_ctrl;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 		ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 		if ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_MASK) &&
79*4882a593Smuzhiyun 				(ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT)) {
80*4882a593Smuzhiyun 			hdmi_i2c->sw_done = true;
81*4882a593Smuzhiyun 			hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
82*4882a593Smuzhiyun 					HDMI_DDC_INT_CTRL_SW_DONE_ACK);
83*4882a593Smuzhiyun 		}
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return hdmi_i2c->sw_done;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
msm_hdmi_i2c_xfer(struct i2c_adapter * i2c,struct i2c_msg * msgs,int num)89*4882a593Smuzhiyun static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
90*4882a593Smuzhiyun 		struct i2c_msg *msgs, int num)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
93*4882a593Smuzhiyun 	struct hdmi *hdmi = hdmi_i2c->hdmi;
94*4882a593Smuzhiyun 	struct drm_device *dev = hdmi->dev;
95*4882a593Smuzhiyun 	static const uint32_t nack[] = {
96*4882a593Smuzhiyun 			HDMI_DDC_SW_STATUS_NACK0, HDMI_DDC_SW_STATUS_NACK1,
97*4882a593Smuzhiyun 			HDMI_DDC_SW_STATUS_NACK2, HDMI_DDC_SW_STATUS_NACK3,
98*4882a593Smuzhiyun 	};
99*4882a593Smuzhiyun 	int indices[MAX_TRANSACTIONS];
100*4882a593Smuzhiyun 	int ret, i, j, index = 0;
101*4882a593Smuzhiyun 	uint32_t ddc_status, ddc_data, i2c_trans;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	num = min(num, MAX_TRANSACTIONS);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE));
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	if (num == 0)
108*4882a593Smuzhiyun 		return num;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	init_ddc(hdmi_i2c);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	ret = ddc_clear_irq(hdmi_i2c);
113*4882a593Smuzhiyun 	if (ret)
114*4882a593Smuzhiyun 		return ret;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
117*4882a593Smuzhiyun 		struct i2c_msg *p = &msgs[i];
118*4882a593Smuzhiyun 		uint32_t raw_addr = p->addr << 1;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 		if (p->flags & I2C_M_RD)
121*4882a593Smuzhiyun 			raw_addr |= 1;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 		ddc_data = HDMI_DDC_DATA_DATA(raw_addr) |
124*4882a593Smuzhiyun 				HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 		if (i == 0) {
127*4882a593Smuzhiyun 			ddc_data |= HDMI_DDC_DATA_INDEX(0) |
128*4882a593Smuzhiyun 					HDMI_DDC_DATA_INDEX_WRITE;
129*4882a593Smuzhiyun 		}
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 		hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
132*4882a593Smuzhiyun 		index++;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		indices[i] = index;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 		if (p->flags & I2C_M_RD) {
137*4882a593Smuzhiyun 			index += p->len;
138*4882a593Smuzhiyun 		} else {
139*4882a593Smuzhiyun 			for (j = 0; j < p->len; j++) {
140*4882a593Smuzhiyun 				ddc_data = HDMI_DDC_DATA_DATA(p->buf[j]) |
141*4882a593Smuzhiyun 						HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
142*4882a593Smuzhiyun 				hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
143*4882a593Smuzhiyun 				index++;
144*4882a593Smuzhiyun 			}
145*4882a593Smuzhiyun 		}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 		i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) |
148*4882a593Smuzhiyun 				HDMI_I2C_TRANSACTION_REG_RW(
149*4882a593Smuzhiyun 						(p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) |
150*4882a593Smuzhiyun 				HDMI_I2C_TRANSACTION_REG_START;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		if (i == (num - 1))
153*4882a593Smuzhiyun 			i2c_trans |= HDMI_I2C_TRANSACTION_REG_STOP;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 		hdmi_write(hdmi, REG_HDMI_I2C_TRANSACTION(i), i2c_trans);
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* trigger the transfer: */
159*4882a593Smuzhiyun 	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
160*4882a593Smuzhiyun 			HDMI_DDC_CTRL_TRANSACTION_CNT(num - 1) |
161*4882a593Smuzhiyun 			HDMI_DDC_CTRL_GO);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	ret = wait_event_timeout(hdmi_i2c->ddc_event, sw_done(hdmi_i2c), HZ/4);
164*4882a593Smuzhiyun 	if (ret <= 0) {
165*4882a593Smuzhiyun 		if (ret == 0)
166*4882a593Smuzhiyun 			ret = -ETIMEDOUT;
167*4882a593Smuzhiyun 		dev_warn(dev->dev, "DDC timeout: %d\n", ret);
168*4882a593Smuzhiyun 		DBG("sw_status=%08x, hw_status=%08x, int_ctrl=%08x",
169*4882a593Smuzhiyun 				hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
170*4882a593Smuzhiyun 				hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
171*4882a593Smuzhiyun 				hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
172*4882a593Smuzhiyun 		return ret;
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* read back results of any read transactions: */
178*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
179*4882a593Smuzhiyun 		struct i2c_msg *p = &msgs[i];
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 		if (!(p->flags & I2C_M_RD))
182*4882a593Smuzhiyun 			continue;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 		/* check for NACK: */
185*4882a593Smuzhiyun 		if (ddc_status & nack[i]) {
186*4882a593Smuzhiyun 			DBG("ddc_status=%08x", ddc_status);
187*4882a593Smuzhiyun 			break;
188*4882a593Smuzhiyun 		}
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 		ddc_data = HDMI_DDC_DATA_DATA_RW(DDC_READ) |
191*4882a593Smuzhiyun 				HDMI_DDC_DATA_INDEX(indices[i]) |
192*4882a593Smuzhiyun 				HDMI_DDC_DATA_INDEX_WRITE;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 		hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 		/* discard first byte: */
197*4882a593Smuzhiyun 		hdmi_read(hdmi, REG_HDMI_DDC_DATA);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 		for (j = 0; j < p->len; j++) {
200*4882a593Smuzhiyun 			ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA);
201*4882a593Smuzhiyun 			p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA);
202*4882a593Smuzhiyun 		}
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	return i;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
msm_hdmi_i2c_func(struct i2c_adapter * adapter)208*4882a593Smuzhiyun static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun static const struct i2c_algorithm msm_hdmi_i2c_algorithm = {
214*4882a593Smuzhiyun 	.master_xfer	= msm_hdmi_i2c_xfer,
215*4882a593Smuzhiyun 	.functionality	= msm_hdmi_i2c_func,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
msm_hdmi_i2c_irq(struct i2c_adapter * i2c)218*4882a593Smuzhiyun void msm_hdmi_i2c_irq(struct i2c_adapter *i2c)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	if (sw_done(hdmi_i2c))
223*4882a593Smuzhiyun 		wake_up_all(&hdmi_i2c->ddc_event);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
msm_hdmi_i2c_destroy(struct i2c_adapter * i2c)226*4882a593Smuzhiyun void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
229*4882a593Smuzhiyun 	i2c_del_adapter(i2c);
230*4882a593Smuzhiyun 	kfree(hdmi_i2c);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
msm_hdmi_i2c_init(struct hdmi * hdmi)233*4882a593Smuzhiyun struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct hdmi_i2c_adapter *hdmi_i2c;
236*4882a593Smuzhiyun 	struct i2c_adapter *i2c = NULL;
237*4882a593Smuzhiyun 	int ret;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	hdmi_i2c = kzalloc(sizeof(*hdmi_i2c), GFP_KERNEL);
240*4882a593Smuzhiyun 	if (!hdmi_i2c) {
241*4882a593Smuzhiyun 		ret = -ENOMEM;
242*4882a593Smuzhiyun 		goto fail;
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	i2c = &hdmi_i2c->base;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	hdmi_i2c->hdmi = hdmi;
248*4882a593Smuzhiyun 	init_waitqueue_head(&hdmi_i2c->ddc_event);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	i2c->owner = THIS_MODULE;
252*4882a593Smuzhiyun 	i2c->class = I2C_CLASS_DDC;
253*4882a593Smuzhiyun 	snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
254*4882a593Smuzhiyun 	i2c->dev.parent = &hdmi->pdev->dev;
255*4882a593Smuzhiyun 	i2c->algo = &msm_hdmi_i2c_algorithm;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	ret = i2c_add_adapter(i2c);
258*4882a593Smuzhiyun 	if (ret)
259*4882a593Smuzhiyun 		goto fail;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	return i2c;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun fail:
264*4882a593Smuzhiyun 	if (i2c)
265*4882a593Smuzhiyun 		msm_hdmi_i2c_destroy(i2c);
266*4882a593Smuzhiyun 	return ERR_PTR(ret);
267*4882a593Smuzhiyun }
268