xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/edp/edp_phy.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include "edp.h"
7*4882a593Smuzhiyun #include "edp.xml.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define EDP_MAX_LANE	4
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun struct edp_phy {
12*4882a593Smuzhiyun 	void __iomem *base;
13*4882a593Smuzhiyun };
14*4882a593Smuzhiyun 
msm_edp_phy_ready(struct edp_phy * phy)15*4882a593Smuzhiyun bool msm_edp_phy_ready(struct edp_phy *phy)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	u32 status;
18*4882a593Smuzhiyun 	int cnt = 100;
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	while (--cnt) {
21*4882a593Smuzhiyun 		status = edp_read(phy->base +
22*4882a593Smuzhiyun 				REG_EDP_PHY_GLB_PHY_STATUS);
23*4882a593Smuzhiyun 		if (status & 0x01)
24*4882a593Smuzhiyun 			break;
25*4882a593Smuzhiyun 		usleep_range(500, 1000);
26*4882a593Smuzhiyun 	}
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	if (cnt == 0) {
29*4882a593Smuzhiyun 		pr_err("%s: PHY NOT ready\n", __func__);
30*4882a593Smuzhiyun 		return false;
31*4882a593Smuzhiyun 	} else {
32*4882a593Smuzhiyun 		return true;
33*4882a593Smuzhiyun 	}
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun 
msm_edp_phy_ctrl(struct edp_phy * phy,int enable)36*4882a593Smuzhiyun void msm_edp_phy_ctrl(struct edp_phy *phy, int enable)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	DBG("enable=%d", enable);
39*4882a593Smuzhiyun 	if (enable) {
40*4882a593Smuzhiyun 		/* Reset */
41*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_CTRL,
42*4882a593Smuzhiyun 			EDP_PHY_CTRL_SW_RESET | EDP_PHY_CTRL_SW_RESET_PLL);
43*4882a593Smuzhiyun 		/* Make sure fully reset */
44*4882a593Smuzhiyun 		wmb();
45*4882a593Smuzhiyun 		usleep_range(500, 1000);
46*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000);
47*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f);
48*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1);
49*4882a593Smuzhiyun 	} else {
50*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0);
51*4882a593Smuzhiyun 	}
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* voltage mode and pre emphasis cfg */
msm_edp_phy_vm_pe_init(struct edp_phy * phy)55*4882a593Smuzhiyun void msm_edp_phy_vm_pe_init(struct edp_phy *phy)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3);
58*4882a593Smuzhiyun 	edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64);
59*4882a593Smuzhiyun 	edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
msm_edp_phy_vm_pe_cfg(struct edp_phy * phy,u32 v0,u32 v1)62*4882a593Smuzhiyun void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0);
65*4882a593Smuzhiyun 	edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
msm_edp_phy_lane_power_ctrl(struct edp_phy * phy,bool up,u32 max_lane)68*4882a593Smuzhiyun void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	u32 i;
71*4882a593Smuzhiyun 	u32 data;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (up)
74*4882a593Smuzhiyun 		data = 0;	/* power up */
75*4882a593Smuzhiyun 	else
76*4882a593Smuzhiyun 		data = 0x7;	/* power down */
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	for (i = 0; i < max_lane; i++)
79*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	/* power down unused lane */
82*4882a593Smuzhiyun 	data = 0x7;	/* power down */
83*4882a593Smuzhiyun 	for (i = max_lane; i < EDP_MAX_LANE; i++)
84*4882a593Smuzhiyun 		edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
msm_edp_phy_init(struct device * dev,void __iomem * regbase)87*4882a593Smuzhiyun void *msm_edp_phy_init(struct device *dev, void __iomem *regbase)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct edp_phy *phy = NULL;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
92*4882a593Smuzhiyun 	if (!phy)
93*4882a593Smuzhiyun 		return NULL;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	phy->base = regbase;
96*4882a593Smuzhiyun 	return phy;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99