xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun #ifndef MMSS_CC_XML
2*4882a593Smuzhiyun #define MMSS_CC_XML
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun /* Autogenerated file, DO NOT EDIT manually!
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun This file was generated by the rules-ng-ng headergen tool in this git repository:
7*4882a593Smuzhiyun http://github.com/freedreno/envytools/
8*4882a593Smuzhiyun git clone https://github.com/freedreno/envytools.git
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun The rules-ng-ng source files this header was generated from are:
11*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2020-07-23 21:58:14)
12*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2020-07-23 21:58:14)
13*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2020-07-23 21:58:14)
14*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2020-07-23 21:58:14)
15*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2020-07-23 21:58:14)
16*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  42301 bytes, from 2020-07-23 21:58:14)
17*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2020-07-23 21:58:14)
18*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2020-07-23 21:58:14)
19*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2020-07-23 21:58:14)
20*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41874 bytes, from 2020-07-23 21:58:14)
21*4882a593Smuzhiyun - /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2020-07-23 21:58:14)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun Copyright (C) 2013-2020 by the following authors:
24*4882a593Smuzhiyun - Rob Clark <robdclark@gmail.com> (robclark)
25*4882a593Smuzhiyun - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun Permission is hereby granted, free of charge, to any person obtaining
28*4882a593Smuzhiyun a copy of this software and associated documentation files (the
29*4882a593Smuzhiyun "Software"), to deal in the Software without restriction, including
30*4882a593Smuzhiyun without limitation the rights to use, copy, modify, merge, publish,
31*4882a593Smuzhiyun distribute, sublicense, and/or sell copies of the Software, and to
32*4882a593Smuzhiyun permit persons to whom the Software is furnished to do so, subject to
33*4882a593Smuzhiyun the following conditions:
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun The above copyright notice and this permission notice (including the
36*4882a593Smuzhiyun next paragraph) shall be included in all copies or substantial
37*4882a593Smuzhiyun portions of the Software.
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40*4882a593Smuzhiyun EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41*4882a593Smuzhiyun MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42*4882a593Smuzhiyun IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43*4882a593Smuzhiyun LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44*4882a593Smuzhiyun OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45*4882a593Smuzhiyun WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun enum mmss_cc_clk {
50*4882a593Smuzhiyun 	CLK = 0,
51*4882a593Smuzhiyun 	PCLK = 1,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define REG_MMSS_CC_AHB						0x00000008
55*4882a593Smuzhiyun 
__offset_CLK(enum mmss_cc_clk idx)56*4882a593Smuzhiyun static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	switch (idx) {
59*4882a593Smuzhiyun 		case CLK: return 0x0000004c;
60*4882a593Smuzhiyun 		case PCLK: return 0x00000130;
61*4882a593Smuzhiyun 		default: return INVALID_IDX(idx);
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun }
REG_MMSS_CC_CLK(enum mmss_cc_clk i0)64*4882a593Smuzhiyun static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
65*4882a593Smuzhiyun 
REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0)66*4882a593Smuzhiyun static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
67*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_CLK_EN					0x00000001
68*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_ROOT_EN					0x00000004
69*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_MND_EN					0x00000020
70*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_MND_MODE__MASK				0x000000c0
71*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_MND_MODE__SHIFT				6
MMSS_CC_CLK_CC_MND_MODE(uint32_t val)72*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_PMXO_SEL__MASK				0x00000300
77*4882a593Smuzhiyun #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT				8
MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)78*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0)83*4882a593Smuzhiyun static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
84*4882a593Smuzhiyun #define MMSS_CC_CLK_MD_D__MASK					0x000000ff
85*4882a593Smuzhiyun #define MMSS_CC_CLK_MD_D__SHIFT					0
MMSS_CC_CLK_MD_D(uint32_t val)86*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun #define MMSS_CC_CLK_MD_M__MASK					0x0000ff00
91*4882a593Smuzhiyun #define MMSS_CC_CLK_MD_M__SHIFT					8
MMSS_CC_CLK_MD_M(uint32_t val)92*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0)97*4882a593Smuzhiyun static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
98*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_SRC__MASK				0x0000000f
99*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_SRC__SHIFT				0
MMSS_CC_CLK_NS_SRC(uint32_t val)100*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK			0x00fff000
105*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT			12
MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)106*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_VAL__MASK				0xff000000
111*4882a593Smuzhiyun #define MMSS_CC_CLK_NS_VAL__SHIFT				24
MMSS_CC_CLK_NS_VAL(uint32_t val)112*4882a593Smuzhiyun static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define REG_MMSS_CC_DSI2_PIXEL_CC				0x00000094
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun #define REG_MMSS_CC_DSI2_PIXEL_NS				0x000000e4
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun #define REG_MMSS_CC_DSI2_PIXEL_CC2				0x00000264
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #endif /* MMSS_CC_XML */
125