1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DP_REG_H_ 7*4882a593Smuzhiyun #define _DP_REG_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* DP_TX Registers */ 10*4882a593Smuzhiyun #define REG_DP_HW_VERSION (0x00000000) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define REG_DP_SW_RESET (0x00000010) 13*4882a593Smuzhiyun #define DP_SW_RESET (0x00000001) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define REG_DP_PHY_CTRL (0x00000014) 16*4882a593Smuzhiyun #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001) 17*4882a593Smuzhiyun #define DP_PHY_CTRL_SW_RESET (0x00000004) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define REG_DP_CLK_CTRL (0x00000018) 20*4882a593Smuzhiyun #define REG_DP_CLK_ACTIVE (0x0000001C) 21*4882a593Smuzhiyun #define REG_DP_INTR_STATUS (0x00000020) 22*4882a593Smuzhiyun #define REG_DP_INTR_STATUS2 (0x00000024) 23*4882a593Smuzhiyun #define REG_DP_INTR_STATUS3 (0x00000028) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define REG_DP_DP_HPD_CTRL (0x00000000) 26*4882a593Smuzhiyun #define DP_DP_HPD_CTRL_HPD_EN (0x00000001) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define REG_DP_DP_HPD_INT_STATUS (0x00000004) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define REG_DP_DP_HPD_INT_ACK (0x00000008) 31*4882a593Smuzhiyun #define DP_DP_HPD_PLUG_INT_ACK (0x00000001) 32*4882a593Smuzhiyun #define DP_DP_IRQ_HPD_INT_ACK (0x00000002) 33*4882a593Smuzhiyun #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004) 34*4882a593Smuzhiyun #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008) 35*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) 36*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define REG_DP_DP_HPD_INT_MASK (0x0000000C) 39*4882a593Smuzhiyun #define DP_DP_HPD_PLUG_INT_MASK (0x00000001) 40*4882a593Smuzhiyun #define DP_DP_IRQ_HPD_INT_MASK (0x00000002) 41*4882a593Smuzhiyun #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) 42*4882a593Smuzhiyun #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) 43*4882a593Smuzhiyun #define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ 44*4882a593Smuzhiyun DP_DP_IRQ_HPD_INT_MASK | \ 45*4882a593Smuzhiyun DP_DP_HPD_REPLUG_INT_MASK | \ 46*4882a593Smuzhiyun DP_DP_HPD_UNPLUG_INT_MASK) 47*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) 48*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) 49*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) 50*4882a593Smuzhiyun #define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define REG_DP_DP_HPD_REFTIMER (0x00000018) 53*4882a593Smuzhiyun #define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) 56*4882a593Smuzhiyun #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) 57*4882a593Smuzhiyun #define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) 58*4882a593Smuzhiyun #define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define REG_DP_AUX_CTRL (0x00000030) 61*4882a593Smuzhiyun #define DP_AUX_CTRL_ENABLE (0x00000001) 62*4882a593Smuzhiyun #define DP_AUX_CTRL_RESET (0x00000002) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define REG_DP_AUX_DATA (0x00000034) 65*4882a593Smuzhiyun #define DP_AUX_DATA_READ (0x00000001) 66*4882a593Smuzhiyun #define DP_AUX_DATA_WRITE (0x00000000) 67*4882a593Smuzhiyun #define DP_AUX_DATA_OFFSET (0x00000008) 68*4882a593Smuzhiyun #define DP_AUX_DATA_INDEX_OFFSET (0x00000010) 69*4882a593Smuzhiyun #define DP_AUX_DATA_MASK (0x0000ff00) 70*4882a593Smuzhiyun #define DP_AUX_DATA_INDEX_WRITE (0x80000000) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define REG_DP_AUX_TRANS_CTRL (0x00000038) 73*4882a593Smuzhiyun #define DP_AUX_TRANS_CTRL_I2C (0x00000100) 74*4882a593Smuzhiyun #define DP_AUX_TRANS_CTRL_GO (0x00000200) 75*4882a593Smuzhiyun #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400) 76*4882a593Smuzhiyun #define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define REG_DP_TIMEOUT_COUNT (0x0000003C) 79*4882a593Smuzhiyun #define REG_DP_AUX_LIMITS (0x00000040) 80*4882a593Smuzhiyun #define REG_DP_AUX_STATUS (0x00000044) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define DP_DPCD_CP_IRQ (0x201) 83*4882a593Smuzhiyun #define DP_DPCD_RXSTATUS (0x69493) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define DP_INTERRUPT_TRANS_NUM (0x000000A0) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define REG_DP_MAINLINK_CTRL (0x00000000) 88*4882a593Smuzhiyun #define DP_MAINLINK_CTRL_ENABLE (0x00000001) 89*4882a593Smuzhiyun #define DP_MAINLINK_CTRL_RESET (0x00000002) 90*4882a593Smuzhiyun #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) 91*4882a593Smuzhiyun #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define REG_DP_STATE_CTRL (0x00000004) 94*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) 95*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002) 96*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004) 97*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008) 98*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010) 99*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_PRBS7 (0x00000020) 100*4882a593Smuzhiyun #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040) 101*4882a593Smuzhiyun #define DP_STATE_CTRL_SEND_VIDEO (0x00000080) 102*4882a593Smuzhiyun #define DP_STATE_CTRL_PUSH_IDLE (0x00000100) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define REG_DP_CONFIGURATION_CTRL (0x00000008) 105*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) 106*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) 107*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) 108*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008) 109*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) 110*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040) 111*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080) 112*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_BPC (0x00000100) 113*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_ASSR (0x00000400) 114*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800) 115*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000) 116*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04) 117*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) 118*4882a593Smuzhiyun #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define REG_DP_SOFTWARE_MVID (0x00000010) 121*4882a593Smuzhiyun #define REG_DP_SOFTWARE_NVID (0x00000018) 122*4882a593Smuzhiyun #define REG_DP_TOTAL_HOR_VER (0x0000001C) 123*4882a593Smuzhiyun #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) 124*4882a593Smuzhiyun #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) 125*4882a593Smuzhiyun #define REG_DP_ACTIVE_HOR_VER (0x00000028) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define REG_DP_MISC1_MISC0 (0x0000002C) 128*4882a593Smuzhiyun #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) 129*4882a593Smuzhiyun #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) 130*4882a593Smuzhiyun #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define REG_DP_VALID_BOUNDARY (0x00000030) 133*4882a593Smuzhiyun #define REG_DP_VALID_BOUNDARY_2 (0x00000034) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038) 136*4882a593Smuzhiyun #define LANE0_MAPPING_SHIFT (0x00000000) 137*4882a593Smuzhiyun #define LANE1_MAPPING_SHIFT (0x00000002) 138*4882a593Smuzhiyun #define LANE2_MAPPING_SHIFT (0x00000004) 139*4882a593Smuzhiyun #define LANE3_MAPPING_SHIFT (0x00000006) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define REG_DP_MAINLINK_READY (0x00000040) 142*4882a593Smuzhiyun #define DP_MAINLINK_READY_FOR_VIDEO (0x00000001) 143*4882a593Smuzhiyun #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define REG_DP_MAINLINK_LEVELS (0x00000044) 146*4882a593Smuzhiyun #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define REG_DP_TU (0x0000004C) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054) 152*4882a593Smuzhiyun #define DP_HBR2_ERM_PATTERN (0x00010000) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0) 155*4882a593Smuzhiyun #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4) 156*4882a593Smuzhiyun #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define MMSS_DP_MISC1_MISC0 (0x0000002C) 159*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080) 160*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084) 161*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088) 162*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C) 163*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090) 164*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094) 165*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define MMSS_DP_PSR_CRC_RG (0x00000154) 168*4882a593Smuzhiyun #define MMSS_DP_PSR_CRC_B (0x00000158) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define REG_DP_COMPRESSION_MODE_CTRL (0x00000180) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define MMSS_DP_AUDIO_CFG (0x00000200) 173*4882a593Smuzhiyun #define MMSS_DP_AUDIO_STATUS (0x00000204) 174*4882a593Smuzhiyun #define MMSS_DP_AUDIO_PKT_CTRL (0x00000208) 175*4882a593Smuzhiyun #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C) 176*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ACR_CTRL (0x00000210) 177*4882a593Smuzhiyun #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define MMSS_DP_SDP_CFG (0x00000228) 180*4882a593Smuzhiyun #define MMSS_DP_SDP_CFG2 (0x0000022C) 181*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) 182*4882a593Smuzhiyun #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define MMSS_DP_AUDIO_STREAM_0 (0x00000240) 185*4882a593Smuzhiyun #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_0 (0x00000250) 188*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_1 (0x00000254) 189*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_2 (0x00000258) 190*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_3 (0x0000025C) 191*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_4 (0x00000260) 192*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_5 (0x00000264) 193*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_6 (0x00000268) 194*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_7 (0x0000026C) 195*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_8 (0x00000270) 196*4882a593Smuzhiyun #define MMSS_DP_EXTENSION_9 (0x00000274) 197*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278) 198*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C) 199*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280) 200*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284) 201*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288) 202*4882a593Smuzhiyun #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C) 203*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_0 (0x00000290) 204*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_1 (0x00000294) 205*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_2 (0x00000298) 206*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_3 (0x0000029C) 207*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0) 208*4882a593Smuzhiyun #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4) 209*4882a593Smuzhiyun #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8) 210*4882a593Smuzhiyun #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC) 211*4882a593Smuzhiyun #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_0 (0x00000300) 214*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_1 (0x00000304) 215*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_2 (0x00000308) 216*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_3 (0x0000030C) 217*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_4 (0x00000310) 218*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_5 (0x00000314) 219*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_6 (0x00000318) 220*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_7 (0x0000031C) 221*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_8 (0x00000320) 222*4882a593Smuzhiyun #define MMSS_DP_GENERIC0_9 (0x00000324) 223*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_0 (0x00000328) 224*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_1 (0x0000032C) 225*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_2 (0x00000330) 226*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_3 (0x00000334) 227*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_4 (0x00000338) 228*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_5 (0x0000033C) 229*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_6 (0x00000340) 230*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_7 (0x00000344) 231*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_8 (0x00000348) 232*4882a593Smuzhiyun #define MMSS_DP_GENERIC1_9 (0x0000034C) 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_0 (0x000002D0) 235*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_1 (0x000002D4) 236*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_2 (0x000002D8) 237*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_3 (0x000002DC) 238*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_4 (0x000002E0) 239*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_5 (0x000002E4) 240*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_6 (0x000002E8) 241*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_7 (0x000002EC) 242*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_8 (0x000002F0) 243*4882a593Smuzhiyun #define MMSS_DP_VSCEXT_9 (0x000002F4) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define MMSS_DP_BIST_ENABLE (0x00000000) 246*4882a593Smuzhiyun #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun #define MMSS_DP_TIMING_ENGINE_EN (0x00000010) 249*4882a593Smuzhiyun #define DP_TIMING_ENGINE_EN_EN (0x00000001) 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define MMSS_DP_INTF_CONFIG (0x00000014) 252*4882a593Smuzhiyun #define MMSS_DP_INTF_HSYNC_CTL (0x00000018) 253*4882a593Smuzhiyun #define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C) 254*4882a593Smuzhiyun #define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020) 255*4882a593Smuzhiyun #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024) 256*4882a593Smuzhiyun #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028) 257*4882a593Smuzhiyun #define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C) 258*4882a593Smuzhiyun #define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030) 259*4882a593Smuzhiyun #define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034) 260*4882a593Smuzhiyun #define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038) 261*4882a593Smuzhiyun #define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C) 262*4882a593Smuzhiyun #define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040) 263*4882a593Smuzhiyun #define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044) 264*4882a593Smuzhiyun #define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048) 265*4882a593Smuzhiyun #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C) 266*4882a593Smuzhiyun #define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050) 267*4882a593Smuzhiyun #define MMSS_DP_INTF_POLARITY_CTL (0x00000058) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #define MMSS_DP_TPG_MAIN_CONTROL (0x00000060) 270*4882a593Smuzhiyun #define MMSS_DP_DSC_DTO (0x0000007C) 271*4882a593Smuzhiyun #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100) 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064) 274*4882a593Smuzhiyun #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) 275*4882a593Smuzhiyun #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) 280*4882a593Smuzhiyun #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) 281*4882a593Smuzhiyun #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun /* DP HDCP 1.3 registers */ 284*4882a593Smuzhiyun #define DP_HDCP_CTRL (0x0A0) 285*4882a593Smuzhiyun #define DP_HDCP_STATUS (0x0A4) 286*4882a593Smuzhiyun #define DP_HDCP_SW_UPPER_AKSV (0x098) 287*4882a593Smuzhiyun #define DP_HDCP_SW_LOWER_AKSV (0x09C) 288*4882a593Smuzhiyun #define DP_HDCP_ENTROPY_CTRL0 (0x350) 289*4882a593Smuzhiyun #define DP_HDCP_ENTROPY_CTRL1 (0x35C) 290*4882a593Smuzhiyun #define DP_HDCP_SHA_STATUS (0x0C8) 291*4882a593Smuzhiyun #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) 292*4882a593Smuzhiyun #define DP_HDCP_RCVPORT_DATA3 (0x0A4) 293*4882a593Smuzhiyun #define DP_HDCP_RCVPORT_DATA4 (0x0A8) 294*4882a593Smuzhiyun #define DP_HDCP_RCVPORT_DATA5 (0x0C0) 295*4882a593Smuzhiyun #define DP_HDCP_RCVPORT_DATA6 (0x0C4) 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) 298*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028) 299*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) 300*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) 301*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) 302*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) 303*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) 304*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) 305*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) 306*4882a593Smuzhiyun #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #endif /* _DP_REG_H_ */ 309