xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dp/dp_panel.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include "dp_panel.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <drm/drm_connector.h>
9*4882a593Smuzhiyun #include <drm/drm_edid.h>
10*4882a593Smuzhiyun #include <drm/drm_print.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun struct dp_panel_private {
13*4882a593Smuzhiyun 	struct device *dev;
14*4882a593Smuzhiyun 	struct dp_panel dp_panel;
15*4882a593Smuzhiyun 	struct drm_dp_aux *aux;
16*4882a593Smuzhiyun 	struct dp_link *link;
17*4882a593Smuzhiyun 	struct dp_catalog *catalog;
18*4882a593Smuzhiyun 	bool panel_on;
19*4882a593Smuzhiyun 	bool aux_cfg_update_done;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
dp_panel_read_dpcd(struct dp_panel * dp_panel)22*4882a593Smuzhiyun static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	int rc = 0;
25*4882a593Smuzhiyun 	size_t len;
26*4882a593Smuzhiyun 	ssize_t rlen;
27*4882a593Smuzhiyun 	struct dp_panel_private *panel;
28*4882a593Smuzhiyun 	struct dp_link_info *link_info;
29*4882a593Smuzhiyun 	u8 *dpcd, major = 0, minor = 0, temp;
30*4882a593Smuzhiyun 	u32 offset = DP_DPCD_REV;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	dpcd = dp_panel->dpcd;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
35*4882a593Smuzhiyun 	link_info = &dp_panel->link_info;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	rlen = drm_dp_dpcd_read(panel->aux, offset,
38*4882a593Smuzhiyun 			dpcd, (DP_RECEIVER_CAP_SIZE + 1));
39*4882a593Smuzhiyun 	if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) {
40*4882a593Smuzhiyun 		DRM_ERROR("dpcd read failed, rlen=%zd\n", rlen);
41*4882a593Smuzhiyun 		if (rlen == -ETIMEDOUT)
42*4882a593Smuzhiyun 			rc = rlen;
43*4882a593Smuzhiyun 		else
44*4882a593Smuzhiyun 			rc = -EINVAL;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 		goto end;
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	temp = dpcd[DP_TRAINING_AUX_RD_INTERVAL];
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	/* check for EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT */
52*4882a593Smuzhiyun 	if (temp & BIT(7)) {
53*4882a593Smuzhiyun 		DRM_DEBUG_DP("using EXTENDED_RECEIVER_CAPABILITY_FIELD\n");
54*4882a593Smuzhiyun 		offset = DPRX_EXTENDED_DPCD_FIELD;
55*4882a593Smuzhiyun 	}
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	rlen = drm_dp_dpcd_read(panel->aux, offset,
58*4882a593Smuzhiyun 		dpcd, (DP_RECEIVER_CAP_SIZE + 1));
59*4882a593Smuzhiyun 	if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) {
60*4882a593Smuzhiyun 		DRM_ERROR("dpcd read failed, rlen=%zd\n", rlen);
61*4882a593Smuzhiyun 		if (rlen == -ETIMEDOUT)
62*4882a593Smuzhiyun 			rc = rlen;
63*4882a593Smuzhiyun 		else
64*4882a593Smuzhiyun 			rc = -EINVAL;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 		goto end;
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	link_info->revision = dpcd[DP_DPCD_REV];
70*4882a593Smuzhiyun 	major = (link_info->revision >> 4) & 0x0f;
71*4882a593Smuzhiyun 	minor = link_info->revision & 0x0f;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
74*4882a593Smuzhiyun 	link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	if (link_info->num_lanes > dp_panel->max_dp_lanes)
77*4882a593Smuzhiyun 		link_info->num_lanes = dp_panel->max_dp_lanes;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* Limit support upto HBR2 until HBR3 support is added */
80*4882a593Smuzhiyun 	if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
81*4882a593Smuzhiyun 		link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	DRM_DEBUG_DP("version: %d.%d\n", major, minor);
84*4882a593Smuzhiyun 	DRM_DEBUG_DP("link_rate=%d\n", link_info->rate);
85*4882a593Smuzhiyun 	DRM_DEBUG_DP("lane_count=%d\n", link_info->num_lanes);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	if (drm_dp_enhanced_frame_cap(dpcd))
88*4882a593Smuzhiyun 		link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	dp_panel->dfp_present = dpcd[DP_DOWNSTREAMPORT_PRESENT];
91*4882a593Smuzhiyun 	dp_panel->dfp_present &= DP_DWN_STRM_PORT_PRESENT;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	if (dp_panel->dfp_present && (dpcd[DP_DPCD_REV] > 0x10)) {
94*4882a593Smuzhiyun 		dp_panel->ds_port_cnt = dpcd[DP_DOWN_STREAM_PORT_COUNT];
95*4882a593Smuzhiyun 		dp_panel->ds_port_cnt &= DP_PORT_COUNT_MASK;
96*4882a593Smuzhiyun 		len = DP_DOWNSTREAM_PORTS * DP_DOWNSTREAM_CAP_SIZE;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 		rlen = drm_dp_dpcd_read(panel->aux,
99*4882a593Smuzhiyun 			DP_DOWNSTREAM_PORT_0, dp_panel->ds_cap_info, len);
100*4882a593Smuzhiyun 		if (rlen < len) {
101*4882a593Smuzhiyun 			DRM_ERROR("ds port status failed, rlen=%zd\n", rlen);
102*4882a593Smuzhiyun 			rc = -EINVAL;
103*4882a593Smuzhiyun 			goto end;
104*4882a593Smuzhiyun 		}
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun end:
108*4882a593Smuzhiyun 	return rc;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
dp_panel_get_supported_bpp(struct dp_panel * dp_panel,u32 mode_edid_bpp,u32 mode_pclk_khz)111*4882a593Smuzhiyun static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
112*4882a593Smuzhiyun 		u32 mode_edid_bpp, u32 mode_pclk_khz)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	struct dp_link_info *link_info;
115*4882a593Smuzhiyun 	const u32 max_supported_bpp = 30, min_supported_bpp = 18;
116*4882a593Smuzhiyun 	u32 bpp = 0, data_rate_khz = 0;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	link_info = &dp_panel->link_info;
121*4882a593Smuzhiyun 	data_rate_khz = link_info->num_lanes * link_info->rate * 8;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	while (bpp > min_supported_bpp) {
124*4882a593Smuzhiyun 		if (mode_pclk_khz * bpp <= data_rate_khz)
125*4882a593Smuzhiyun 			break;
126*4882a593Smuzhiyun 		bpp -= 6;
127*4882a593Smuzhiyun 	}
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	return bpp;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
dp_panel_update_modes(struct drm_connector * connector,struct edid * edid)132*4882a593Smuzhiyun static int dp_panel_update_modes(struct drm_connector *connector,
133*4882a593Smuzhiyun 	struct edid *edid)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	int rc = 0;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (edid) {
138*4882a593Smuzhiyun 		rc = drm_connector_update_edid_property(connector, edid);
139*4882a593Smuzhiyun 		if (rc) {
140*4882a593Smuzhiyun 			DRM_ERROR("failed to update edid property %d\n", rc);
141*4882a593Smuzhiyun 			return rc;
142*4882a593Smuzhiyun 		}
143*4882a593Smuzhiyun 		rc = drm_add_edid_modes(connector, edid);
144*4882a593Smuzhiyun 		DRM_DEBUG_DP("%s -", __func__);
145*4882a593Smuzhiyun 		return rc;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	rc = drm_connector_update_edid_property(connector, NULL);
149*4882a593Smuzhiyun 	if (rc)
150*4882a593Smuzhiyun 		DRM_ERROR("failed to update edid property %d\n", rc);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return rc;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
dp_panel_read_sink_caps(struct dp_panel * dp_panel,struct drm_connector * connector)155*4882a593Smuzhiyun int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
156*4882a593Smuzhiyun 	struct drm_connector *connector)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	int rc = 0, bw_code;
159*4882a593Smuzhiyun 	int rlen, count;
160*4882a593Smuzhiyun 	struct dp_panel_private *panel;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (!dp_panel || !connector) {
163*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
164*4882a593Smuzhiyun 		return -EINVAL;
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	rc = dp_panel_read_dpcd(dp_panel);
170*4882a593Smuzhiyun 	bw_code = drm_dp_link_rate_to_bw_code(dp_panel->link_info.rate);
171*4882a593Smuzhiyun 	if (rc || !is_link_rate_valid(bw_code) ||
172*4882a593Smuzhiyun 			!is_lane_count_valid(dp_panel->link_info.num_lanes) ||
173*4882a593Smuzhiyun 			(bw_code > dp_panel->max_bw_code)) {
174*4882a593Smuzhiyun 		DRM_ERROR("read dpcd failed %d\n", rc);
175*4882a593Smuzhiyun 		return rc;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if (dp_panel->dfp_present) {
179*4882a593Smuzhiyun 		rlen = drm_dp_dpcd_read(panel->aux, DP_SINK_COUNT,
180*4882a593Smuzhiyun 				&count, 1);
181*4882a593Smuzhiyun 		if (rlen == 1) {
182*4882a593Smuzhiyun 			count = DP_GET_SINK_COUNT(count);
183*4882a593Smuzhiyun 			if (!count) {
184*4882a593Smuzhiyun 				DRM_ERROR("no downstream ports connected\n");
185*4882a593Smuzhiyun 				panel->link->sink_count = 0;
186*4882a593Smuzhiyun 				rc = -ENOTCONN;
187*4882a593Smuzhiyun 				goto end;
188*4882a593Smuzhiyun 			}
189*4882a593Smuzhiyun 		}
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	kfree(dp_panel->edid);
193*4882a593Smuzhiyun 	dp_panel->edid = NULL;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	dp_panel->edid = drm_get_edid(connector,
196*4882a593Smuzhiyun 					      &panel->aux->ddc);
197*4882a593Smuzhiyun 	if (!dp_panel->edid) {
198*4882a593Smuzhiyun 		DRM_ERROR("panel edid read failed\n");
199*4882a593Smuzhiyun 		/* check edid read fail is due to unplug */
200*4882a593Smuzhiyun 		if (!dp_catalog_link_is_connected(panel->catalog)) {
201*4882a593Smuzhiyun 			rc = -ETIMEDOUT;
202*4882a593Smuzhiyun 			goto end;
203*4882a593Smuzhiyun 		}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 		/* fail safe edid */
206*4882a593Smuzhiyun 		mutex_lock(&connector->dev->mode_config.mutex);
207*4882a593Smuzhiyun 		if (drm_add_modes_noedid(connector, 640, 480))
208*4882a593Smuzhiyun 			drm_set_preferred_mode(connector, 640, 480);
209*4882a593Smuzhiyun 		mutex_unlock(&connector->dev->mode_config.mutex);
210*4882a593Smuzhiyun 	}
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if (panel->aux_cfg_update_done) {
213*4882a593Smuzhiyun 		DRM_DEBUG_DP("read DPCD with updated AUX config\n");
214*4882a593Smuzhiyun 		rc = dp_panel_read_dpcd(dp_panel);
215*4882a593Smuzhiyun 		bw_code = drm_dp_link_rate_to_bw_code(dp_panel->link_info.rate);
216*4882a593Smuzhiyun 		if (rc || !is_link_rate_valid(bw_code) ||
217*4882a593Smuzhiyun 			!is_lane_count_valid(dp_panel->link_info.num_lanes)
218*4882a593Smuzhiyun 			|| (bw_code > dp_panel->max_bw_code)) {
219*4882a593Smuzhiyun 			DRM_ERROR("read dpcd failed %d\n", rc);
220*4882a593Smuzhiyun 			return rc;
221*4882a593Smuzhiyun 		}
222*4882a593Smuzhiyun 		panel->aux_cfg_update_done = false;
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun end:
225*4882a593Smuzhiyun 	return rc;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
dp_panel_get_mode_bpp(struct dp_panel * dp_panel,u32 mode_edid_bpp,u32 mode_pclk_khz)228*4882a593Smuzhiyun u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel,
229*4882a593Smuzhiyun 		u32 mode_edid_bpp, u32 mode_pclk_khz)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	struct dp_panel_private *panel;
232*4882a593Smuzhiyun 	u32 bpp = mode_edid_bpp;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	if (!dp_panel || !mode_edid_bpp || !mode_pclk_khz) {
235*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
236*4882a593Smuzhiyun 		return 0;
237*4882a593Smuzhiyun 	}
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	if (dp_panel->video_test)
242*4882a593Smuzhiyun 		bpp = dp_link_bit_depth_to_bpp(
243*4882a593Smuzhiyun 				panel->link->test_video.test_bit_depth);
244*4882a593Smuzhiyun 	else
245*4882a593Smuzhiyun 		bpp = dp_panel_get_supported_bpp(dp_panel, mode_edid_bpp,
246*4882a593Smuzhiyun 				mode_pclk_khz);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	return bpp;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun 
dp_panel_get_modes(struct dp_panel * dp_panel,struct drm_connector * connector,struct dp_display_mode * mode)251*4882a593Smuzhiyun int dp_panel_get_modes(struct dp_panel *dp_panel,
252*4882a593Smuzhiyun 	struct drm_connector *connector, struct dp_display_mode *mode)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	if (!dp_panel) {
255*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
256*4882a593Smuzhiyun 		return -EINVAL;
257*4882a593Smuzhiyun 	}
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	if (dp_panel->edid)
260*4882a593Smuzhiyun 		return dp_panel_update_modes(connector, dp_panel->edid);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	return 0;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
dp_panel_get_edid_checksum(struct edid * edid)265*4882a593Smuzhiyun static u8 dp_panel_get_edid_checksum(struct edid *edid)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	struct edid *last_block;
268*4882a593Smuzhiyun 	u8 *raw_edid;
269*4882a593Smuzhiyun 	bool is_edid_corrupt = false;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (!edid) {
272*4882a593Smuzhiyun 		DRM_ERROR("invalid edid input\n");
273*4882a593Smuzhiyun 		return 0;
274*4882a593Smuzhiyun 	}
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	raw_edid = (u8 *)edid;
277*4882a593Smuzhiyun 	raw_edid += (edid->extensions * EDID_LENGTH);
278*4882a593Smuzhiyun 	last_block = (struct edid *)raw_edid;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	/* block type extension */
281*4882a593Smuzhiyun 	drm_edid_block_valid(raw_edid, 1, false, &is_edid_corrupt);
282*4882a593Smuzhiyun 	if (!is_edid_corrupt)
283*4882a593Smuzhiyun 		return last_block->checksum;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	DRM_ERROR("Invalid block, no checksum\n");
286*4882a593Smuzhiyun 	return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun 
dp_panel_handle_sink_request(struct dp_panel * dp_panel)289*4882a593Smuzhiyun void dp_panel_handle_sink_request(struct dp_panel *dp_panel)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun 	struct dp_panel_private *panel;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (!dp_panel) {
294*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
295*4882a593Smuzhiyun 		return;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) {
301*4882a593Smuzhiyun 		u8 checksum;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 		if (dp_panel->edid)
304*4882a593Smuzhiyun 			checksum = dp_panel_get_edid_checksum(dp_panel->edid);
305*4882a593Smuzhiyun 		else
306*4882a593Smuzhiyun 			checksum = dp_panel->connector->real_edid_checksum;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 		dp_link_send_edid_checksum(panel->link, checksum);
309*4882a593Smuzhiyun 		dp_link_send_test_response(panel->link);
310*4882a593Smuzhiyun 	}
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
dp_panel_tpg_config(struct dp_panel * dp_panel,bool enable)313*4882a593Smuzhiyun void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun 	struct dp_catalog *catalog;
316*4882a593Smuzhiyun 	struct dp_panel_private *panel;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	if (!dp_panel) {
319*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
320*4882a593Smuzhiyun 		return;
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
324*4882a593Smuzhiyun 	catalog = panel->catalog;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	if (!panel->panel_on) {
327*4882a593Smuzhiyun 		DRM_DEBUG_DP("DP panel not enabled, handle TPG on next on\n");
328*4882a593Smuzhiyun 		return;
329*4882a593Smuzhiyun 	}
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	if (!enable) {
332*4882a593Smuzhiyun 		dp_catalog_panel_tpg_disable(catalog);
333*4882a593Smuzhiyun 		return;
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	DRM_DEBUG_DP("%s: calling catalog tpg_enable\n", __func__);
337*4882a593Smuzhiyun 	dp_catalog_panel_tpg_enable(catalog, &panel->dp_panel.dp_mode.drm_mode);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
dp_panel_dump_regs(struct dp_panel * dp_panel)340*4882a593Smuzhiyun void dp_panel_dump_regs(struct dp_panel *dp_panel)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct dp_catalog *catalog;
343*4882a593Smuzhiyun 	struct dp_panel_private *panel;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
346*4882a593Smuzhiyun 	catalog = panel->catalog;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	dp_catalog_dump_regs(catalog);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
dp_panel_timing_cfg(struct dp_panel * dp_panel)351*4882a593Smuzhiyun int dp_panel_timing_cfg(struct dp_panel *dp_panel)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	int rc = 0;
354*4882a593Smuzhiyun 	u32 data, total_ver, total_hor;
355*4882a593Smuzhiyun 	struct dp_catalog *catalog;
356*4882a593Smuzhiyun 	struct dp_panel_private *panel;
357*4882a593Smuzhiyun 	struct drm_display_mode *drm_mode;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
360*4882a593Smuzhiyun 	catalog = panel->catalog;
361*4882a593Smuzhiyun 	drm_mode = &panel->dp_panel.dp_mode.drm_mode;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	DRM_DEBUG_DP("width=%d hporch= %d %d %d\n",
364*4882a593Smuzhiyun 		drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end,
365*4882a593Smuzhiyun 		drm_mode->hsync_start - drm_mode->hdisplay,
366*4882a593Smuzhiyun 		drm_mode->hsync_end - drm_mode->hsync_start);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	DRM_DEBUG_DP("height=%d vporch= %d %d %d\n",
369*4882a593Smuzhiyun 		drm_mode->vdisplay, drm_mode->vtotal - drm_mode->vsync_end,
370*4882a593Smuzhiyun 		drm_mode->vsync_start - drm_mode->vdisplay,
371*4882a593Smuzhiyun 		drm_mode->vsync_end - drm_mode->vsync_start);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	total_hor = drm_mode->htotal;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	total_ver = drm_mode->vtotal;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	data = total_ver;
378*4882a593Smuzhiyun 	data <<= 16;
379*4882a593Smuzhiyun 	data |= total_hor;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	catalog->total = data;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	data = (drm_mode->vtotal - drm_mode->vsync_start);
384*4882a593Smuzhiyun 	data <<= 16;
385*4882a593Smuzhiyun 	data |= (drm_mode->htotal - drm_mode->hsync_start);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	catalog->sync_start = data;
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	data = drm_mode->vsync_end - drm_mode->vsync_start;
390*4882a593Smuzhiyun 	data <<= 16;
391*4882a593Smuzhiyun 	data |= (panel->dp_panel.dp_mode.v_active_low << 31);
392*4882a593Smuzhiyun 	data |= drm_mode->hsync_end - drm_mode->hsync_start;
393*4882a593Smuzhiyun 	data |= (panel->dp_panel.dp_mode.h_active_low << 15);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	catalog->width_blanking = data;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	data = drm_mode->vdisplay;
398*4882a593Smuzhiyun 	data <<= 16;
399*4882a593Smuzhiyun 	data |= drm_mode->hdisplay;
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	catalog->dp_active = data;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	dp_catalog_panel_timing_cfg(catalog);
404*4882a593Smuzhiyun 	panel->panel_on = true;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	return rc;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun 
dp_panel_init_panel_info(struct dp_panel * dp_panel)409*4882a593Smuzhiyun int dp_panel_init_panel_info(struct dp_panel *dp_panel)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun 	int rc = 0;
412*4882a593Smuzhiyun 	struct drm_display_mode *drm_mode;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	drm_mode = &dp_panel->dp_mode.drm_mode;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	/*
417*4882a593Smuzhiyun 	 * print resolution info as this is a result
418*4882a593Smuzhiyun 	 * of user initiated action of cable connection
419*4882a593Smuzhiyun 	 */
420*4882a593Smuzhiyun 	DRM_DEBUG_DP("SET NEW RESOLUTION:\n");
421*4882a593Smuzhiyun 	DRM_DEBUG_DP("%dx%d@%dfps\n", drm_mode->hdisplay,
422*4882a593Smuzhiyun 		drm_mode->vdisplay, drm_mode_vrefresh(drm_mode));
423*4882a593Smuzhiyun 	DRM_DEBUG_DP("h_porches(back|front|width) = (%d|%d|%d)\n",
424*4882a593Smuzhiyun 			drm_mode->htotal - drm_mode->hsync_end,
425*4882a593Smuzhiyun 			drm_mode->hsync_start - drm_mode->hdisplay,
426*4882a593Smuzhiyun 			drm_mode->hsync_end - drm_mode->hsync_start);
427*4882a593Smuzhiyun 	DRM_DEBUG_DP("v_porches(back|front|width) = (%d|%d|%d)\n",
428*4882a593Smuzhiyun 			drm_mode->vtotal - drm_mode->vsync_end,
429*4882a593Smuzhiyun 			drm_mode->vsync_start - drm_mode->vdisplay,
430*4882a593Smuzhiyun 			drm_mode->vsync_end - drm_mode->vsync_start);
431*4882a593Smuzhiyun 	DRM_DEBUG_DP("pixel clock (KHz)=(%d)\n", drm_mode->clock);
432*4882a593Smuzhiyun 	DRM_DEBUG_DP("bpp = %d\n", dp_panel->dp_mode.bpp);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	dp_panel->dp_mode.bpp = max_t(u32, 18,
435*4882a593Smuzhiyun 					min_t(u32, dp_panel->dp_mode.bpp, 30));
436*4882a593Smuzhiyun 	DRM_DEBUG_DP("updated bpp = %d\n", dp_panel->dp_mode.bpp);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	return rc;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun 
dp_panel_get(struct dp_panel_in * in)441*4882a593Smuzhiyun struct dp_panel *dp_panel_get(struct dp_panel_in *in)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun 	struct dp_panel_private *panel;
444*4882a593Smuzhiyun 	struct dp_panel *dp_panel;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	if (!in->dev || !in->catalog || !in->aux || !in->link) {
447*4882a593Smuzhiyun 		DRM_ERROR("invalid input\n");
448*4882a593Smuzhiyun 		return ERR_PTR(-EINVAL);
449*4882a593Smuzhiyun 	}
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	panel = devm_kzalloc(in->dev, sizeof(*panel), GFP_KERNEL);
452*4882a593Smuzhiyun 	if (!panel)
453*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	panel->dev = in->dev;
456*4882a593Smuzhiyun 	panel->aux = in->aux;
457*4882a593Smuzhiyun 	panel->catalog = in->catalog;
458*4882a593Smuzhiyun 	panel->link = in->link;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	dp_panel = &panel->dp_panel;
461*4882a593Smuzhiyun 	dp_panel->max_bw_code = DP_LINK_BW_8_1;
462*4882a593Smuzhiyun 	panel->aux_cfg_update_done = false;
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	return dp_panel;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
dp_panel_put(struct dp_panel * dp_panel)467*4882a593Smuzhiyun void dp_panel_put(struct dp_panel *dp_panel)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	if (!dp_panel)
470*4882a593Smuzhiyun 		return;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	kfree(dp_panel->edid);
473*4882a593Smuzhiyun }
474