xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dp/dp_link.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _DP_LINK_H_
7*4882a593Smuzhiyun #define _DP_LINK_H_
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "dp_aux.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define DS_PORT_STATUS_CHANGED 0x200
12*4882a593Smuzhiyun #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
13*4882a593Smuzhiyun #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct dp_link_info {
16*4882a593Smuzhiyun 	unsigned char revision;
17*4882a593Smuzhiyun 	unsigned int rate;
18*4882a593Smuzhiyun 	unsigned int num_lanes;
19*4882a593Smuzhiyun 	unsigned long capabilities;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun enum dp_link_voltage_level {
23*4882a593Smuzhiyun 	DP_TRAIN_VOLTAGE_SWING_LVL_0	= 0,
24*4882a593Smuzhiyun 	DP_TRAIN_VOLTAGE_SWING_LVL_1	= 1,
25*4882a593Smuzhiyun 	DP_TRAIN_VOLTAGE_SWING_LVL_2	= 2,
26*4882a593Smuzhiyun 	DP_TRAIN_VOLTAGE_SWING_MAX	= DP_TRAIN_VOLTAGE_SWING_LVL_2,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun enum dp_link_preemaphasis_level {
30*4882a593Smuzhiyun 	DP_TRAIN_PRE_EMPHASIS_LVL_0	= 0,
31*4882a593Smuzhiyun 	DP_TRAIN_PRE_EMPHASIS_LVL_1	= 1,
32*4882a593Smuzhiyun 	DP_TRAIN_PRE_EMPHASIS_LVL_2	= 2,
33*4882a593Smuzhiyun 	DP_TRAIN_PRE_EMPHASIS_MAX	= DP_TRAIN_PRE_EMPHASIS_LVL_2,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun struct dp_link_test_video {
37*4882a593Smuzhiyun 	u32 test_video_pattern;
38*4882a593Smuzhiyun 	u32 test_bit_depth;
39*4882a593Smuzhiyun 	u32 test_dyn_range;
40*4882a593Smuzhiyun 	u32 test_h_total;
41*4882a593Smuzhiyun 	u32 test_v_total;
42*4882a593Smuzhiyun 	u32 test_h_start;
43*4882a593Smuzhiyun 	u32 test_v_start;
44*4882a593Smuzhiyun 	u32 test_hsync_pol;
45*4882a593Smuzhiyun 	u32 test_hsync_width;
46*4882a593Smuzhiyun 	u32 test_vsync_pol;
47*4882a593Smuzhiyun 	u32 test_vsync_width;
48*4882a593Smuzhiyun 	u32 test_h_width;
49*4882a593Smuzhiyun 	u32 test_v_height;
50*4882a593Smuzhiyun 	u32 test_rr_d;
51*4882a593Smuzhiyun 	u32 test_rr_n;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun struct dp_link_test_audio {
55*4882a593Smuzhiyun 	u32 test_audio_sampling_rate;
56*4882a593Smuzhiyun 	u32 test_audio_channel_count;
57*4882a593Smuzhiyun 	u32 test_audio_pattern_type;
58*4882a593Smuzhiyun 	u32 test_audio_period_ch_1;
59*4882a593Smuzhiyun 	u32 test_audio_period_ch_2;
60*4882a593Smuzhiyun 	u32 test_audio_period_ch_3;
61*4882a593Smuzhiyun 	u32 test_audio_period_ch_4;
62*4882a593Smuzhiyun 	u32 test_audio_period_ch_5;
63*4882a593Smuzhiyun 	u32 test_audio_period_ch_6;
64*4882a593Smuzhiyun 	u32 test_audio_period_ch_7;
65*4882a593Smuzhiyun 	u32 test_audio_period_ch_8;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun struct dp_link_phy_params {
69*4882a593Smuzhiyun 	u32 phy_test_pattern_sel;
70*4882a593Smuzhiyun 	u8 v_level;
71*4882a593Smuzhiyun 	u8 p_level;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct dp_link {
75*4882a593Smuzhiyun 	u32 sink_request;
76*4882a593Smuzhiyun 	u32 test_response;
77*4882a593Smuzhiyun 	bool psm_enabled;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	u8 sink_count;
80*4882a593Smuzhiyun 	struct dp_link_test_video test_video;
81*4882a593Smuzhiyun 	struct dp_link_test_audio test_audio;
82*4882a593Smuzhiyun 	struct dp_link_phy_params phy_params;
83*4882a593Smuzhiyun 	struct dp_link_info link_params;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun  * mdss_dp_test_bit_depth_to_bpp() - convert test bit depth to bpp
88*4882a593Smuzhiyun  * @tbd: test bit depth
89*4882a593Smuzhiyun  *
90*4882a593Smuzhiyun  * Returns the bits per pixel (bpp) to be used corresponding to the
91*4882a593Smuzhiyun  * git bit depth value. This function assumes that bit depth has
92*4882a593Smuzhiyun  * already been validated.
93*4882a593Smuzhiyun  */
dp_link_bit_depth_to_bpp(u32 tbd)94*4882a593Smuzhiyun static inline u32 dp_link_bit_depth_to_bpp(u32 tbd)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	/*
97*4882a593Smuzhiyun 	 * Few simplistic rules and assumptions made here:
98*4882a593Smuzhiyun 	 *    1. Bit depth is per color component
99*4882a593Smuzhiyun 	 *    2. If bit depth is unknown return 0
100*4882a593Smuzhiyun 	 *    3. Assume 3 color components
101*4882a593Smuzhiyun 	 */
102*4882a593Smuzhiyun 	switch (tbd) {
103*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_6:
104*4882a593Smuzhiyun 		return 18;
105*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_8:
106*4882a593Smuzhiyun 		return 24;
107*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_10:
108*4882a593Smuzhiyun 		return 30;
109*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_UNKNOWN:
110*4882a593Smuzhiyun 	default:
111*4882a593Smuzhiyun 		return 0;
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /**
116*4882a593Smuzhiyun  * dp_test_bit_depth_to_bpc() - convert test bit depth to bpc
117*4882a593Smuzhiyun  * @tbd: test bit depth
118*4882a593Smuzhiyun  *
119*4882a593Smuzhiyun  * Returns the bits per comp (bpc) to be used corresponding to the
120*4882a593Smuzhiyun  * bit depth value. This function assumes that bit depth has
121*4882a593Smuzhiyun  * already been validated.
122*4882a593Smuzhiyun  */
dp_link_bit_depth_to_bpc(u32 tbd)123*4882a593Smuzhiyun static inline u32 dp_link_bit_depth_to_bpc(u32 tbd)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	switch (tbd) {
126*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_6:
127*4882a593Smuzhiyun 		return 6;
128*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_8:
129*4882a593Smuzhiyun 		return 8;
130*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_10:
131*4882a593Smuzhiyun 		return 10;
132*4882a593Smuzhiyun 	case DP_TEST_BIT_DEPTH_UNKNOWN:
133*4882a593Smuzhiyun 	default:
134*4882a593Smuzhiyun 		return 0;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link);
139*4882a593Smuzhiyun u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp);
140*4882a593Smuzhiyun int dp_link_process_request(struct dp_link *dp_link);
141*4882a593Smuzhiyun int dp_link_get_colorimetry_config(struct dp_link *dp_link);
142*4882a593Smuzhiyun int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status);
143*4882a593Smuzhiyun bool dp_link_send_test_response(struct dp_link *dp_link);
144*4882a593Smuzhiyun int dp_link_psm_config(struct dp_link *dp_link,
145*4882a593Smuzhiyun 		struct dp_link_info *link_info, bool enable);
146*4882a593Smuzhiyun bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /**
149*4882a593Smuzhiyun  * dp_link_get() - get the functionalities of dp test module
150*4882a593Smuzhiyun  *
151*4882a593Smuzhiyun  *
152*4882a593Smuzhiyun  * return: a pointer to dp_link struct
153*4882a593Smuzhiyun  */
154*4882a593Smuzhiyun struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #endif /* _DP_LINK_H_ */
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