1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 BayLibre, SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Video Input Unit */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MESON_VIU_H 10*4882a593Smuzhiyun #define __MESON_VIU_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* OSDx_BLKx_CFG */ 13*4882a593Smuzhiyun #define OSD_MALI_SRC_EN BIT(30) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define OSD_CANVAS_SEL 16 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define OSD_ENDIANNESS_LE BIT(15) 18*4882a593Smuzhiyun #define OSD_ENDIANNESS_BE (0) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define OSD_BLK_MODE_422 (0x03 << 8) 21*4882a593Smuzhiyun #define OSD_BLK_MODE_16 (0x04 << 8) 22*4882a593Smuzhiyun #define OSD_BLK_MODE_32 (0x05 << 8) 23*4882a593Smuzhiyun #define OSD_BLK_MODE_24 (0x07 << 8) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define OSD_OUTPUT_COLOR_RGB BIT(7) 26*4882a593Smuzhiyun #define OSD_OUTPUT_COLOR_YUV (0) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2) 29*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2) 30*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2) 31*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_24_RGB (0x00 << 2) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2) 36*4882a593Smuzhiyun #define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_R8 (0 << 8) 39*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_YUV422 (1 << 8) 40*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGB565 (2 << 8) 41*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGBA5551 (3 << 8) 42*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGBA4444 (4 << 8) 43*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGBA8888 (5 << 8) 44*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGB888 (7 << 8) 45*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_YUV422_10B (8 << 8) 46*4882a593Smuzhiyun #define OSD_MALI_COLOR_MODE_RGBA1010102 (9 << 8) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define OSD_INTERLACE_ENABLED BIT(1) 49*4882a593Smuzhiyun #define OSD_INTERLACE_ODD BIT(0) 50*4882a593Smuzhiyun #define OSD_INTERLACE_EVEN (0) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* OSDx_CTRL_STAT */ 53*4882a593Smuzhiyun #define OSD_ENABLE BIT(21) 54*4882a593Smuzhiyun #define OSD_MEM_LINEAR_ADDR BIT(2) 55*4882a593Smuzhiyun #define OSD_BLK0_ENABLE BIT(0) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define OSD_GLOBAL_ALPHA_SHIFT 12 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* OSDx_CTRL_STAT2 */ 60*4882a593Smuzhiyun #define OSD_DPATH_MALI_AFBCD BIT(15) 61*4882a593Smuzhiyun #define OSD_REPLACE_EN BIT(14) 62*4882a593Smuzhiyun #define OSD_REPLACE_SHIFT 6 63*4882a593Smuzhiyun #define OSD_PENDING_STAT_CLEAN BIT(1) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun void meson_viu_osd1_reset(struct meson_drm *priv); 66*4882a593Smuzhiyun void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv); 67*4882a593Smuzhiyun void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv); 68*4882a593Smuzhiyun void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv); 69*4882a593Smuzhiyun void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv); 70*4882a593Smuzhiyun void meson_viu_init(struct meson_drm *priv); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __MESON_VIU_H */ 73