1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 BayLibre, SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Video Clock */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MESON_VCLK_H 10*4882a593Smuzhiyun #define __MESON_VCLK_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <drm/drm_modes.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct meson_drm; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum { 17*4882a593Smuzhiyun MESON_VCLK_TARGET_CVBS = 0, 18*4882a593Smuzhiyun MESON_VCLK_TARGET_HDMI = 1, 19*4882a593Smuzhiyun MESON_VCLK_TARGET_DMT = 2, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 27MHz is the CVBS Pixel Clock */ 23*4882a593Smuzhiyun #define MESON_VCLK_CVBS 27000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum drm_mode_status 26*4882a593Smuzhiyun meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); 27*4882a593Smuzhiyun enum drm_mode_status 28*4882a593Smuzhiyun meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, 29*4882a593Smuzhiyun unsigned int vclk_freq); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun void meson_vclk_setup(struct meson_drm *priv, unsigned int target, 32*4882a593Smuzhiyun unsigned int phy_freq, unsigned int vclk_freq, 33*4882a593Smuzhiyun unsigned int venc_freq, unsigned int dac_freq, 34*4882a593Smuzhiyun bool hdmi_use_enci); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __MESON_VCLK_H */ 37