xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/meson_osd_afbcd.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2019 BayLibre, SAS
4*4882a593Smuzhiyun  * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __MESON_OSD_AFBCD_H
8*4882a593Smuzhiyun #define __MESON_OSD_AFBCD_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include "meson_drv.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* This is an internal address used to transfer pixel from AFBC to the VIU */
13*4882a593Smuzhiyun #define MESON_G12A_AFBCD_OUT_ADDR	0x1000000
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct meson_afbcd_ops {
16*4882a593Smuzhiyun 	int (*init)(struct meson_drm *priv);
17*4882a593Smuzhiyun 	void (*exit)(struct meson_drm *priv);
18*4882a593Smuzhiyun 	int (*reset)(struct meson_drm *priv);
19*4882a593Smuzhiyun 	int (*enable)(struct meson_drm *priv);
20*4882a593Smuzhiyun 	int (*disable)(struct meson_drm *priv);
21*4882a593Smuzhiyun 	int (*setup)(struct meson_drm *priv);
22*4882a593Smuzhiyun 	int (*fmt_to_blk_mode)(u64 modifier, uint32_t format);
23*4882a593Smuzhiyun 	bool (*supported_fmt)(u64 modifier, uint32_t format);
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun extern struct meson_afbcd_ops meson_afbcd_gxm_ops;
27*4882a593Smuzhiyun extern struct meson_afbcd_ops meson_afbcd_g12a_ops;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #endif /* __MESON_OSD_AFBCD_H */
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