1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 BayLibre, SAS
4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun * Copyright (C) 2014 Endless Mobile
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Written by:
8*4882a593Smuzhiyun * Jasper St. Pierre <jstpierre@mecheye.net>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/component.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_graph.h>
14*4882a593Smuzhiyun #include <linux/sys_soc.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/soc/amlogic/meson-canvas.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_drv.h>
20*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_irq.h>
24*4882a593Smuzhiyun #include <drm/drm_modeset_helper_vtables.h>
25*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
26*4882a593Smuzhiyun #include <drm/drm_vblank.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include "meson_crtc.h"
29*4882a593Smuzhiyun #include "meson_drv.h"
30*4882a593Smuzhiyun #include "meson_overlay.h"
31*4882a593Smuzhiyun #include "meson_plane.h"
32*4882a593Smuzhiyun #include "meson_osd_afbcd.h"
33*4882a593Smuzhiyun #include "meson_registers.h"
34*4882a593Smuzhiyun #include "meson_venc_cvbs.h"
35*4882a593Smuzhiyun #include "meson_viu.h"
36*4882a593Smuzhiyun #include "meson_vpp.h"
37*4882a593Smuzhiyun #include "meson_rdma.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define DRIVER_NAME "meson"
40*4882a593Smuzhiyun #define DRIVER_DESC "Amlogic Meson DRM driver"
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /**
43*4882a593Smuzhiyun * DOC: Video Processing Unit
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * VPU Handles the Global Video Processing, it includes management of the
46*4882a593Smuzhiyun * clocks gates, blocks reset lines and power domains.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * What is missing :
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * - Full reset of entire video processing HW blocks
51*4882a593Smuzhiyun * - Scaling and setup of the VPU clock
52*4882a593Smuzhiyun * - Bus clock gates
53*4882a593Smuzhiyun * - Powering up video processing HW blocks
54*4882a593Smuzhiyun * - Powering Up HDMI controller and PHY
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static const struct drm_mode_config_funcs meson_mode_config_funcs = {
58*4882a593Smuzhiyun .atomic_check = drm_atomic_helper_check,
59*4882a593Smuzhiyun .atomic_commit = drm_atomic_helper_commit,
60*4882a593Smuzhiyun .fb_create = drm_gem_fb_create,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
64*4882a593Smuzhiyun .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
meson_irq(int irq,void * arg)67*4882a593Smuzhiyun static irqreturn_t meson_irq(int irq, void *arg)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct drm_device *dev = arg;
70*4882a593Smuzhiyun struct meson_drm *priv = dev->dev_private;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun meson_crtc_irq(priv);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return IRQ_HANDLED;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
meson_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)79*4882a593Smuzhiyun static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
80*4882a593Smuzhiyun struct drm_mode_create_dumb *args)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * We need 64bytes aligned stride, and PAGE aligned size
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
86*4882a593Smuzhiyun args->size = PAGE_ALIGN(args->pitch * args->height);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return drm_gem_cma_dumb_create_internal(file, dev, args);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(fops);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static struct drm_driver meson_driver = {
94*4882a593Smuzhiyun .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* IRQ */
97*4882a593Smuzhiyun .irq_handler = meson_irq,
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* CMA Ops */
100*4882a593Smuzhiyun DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Misc */
103*4882a593Smuzhiyun .fops = &fops,
104*4882a593Smuzhiyun .name = DRIVER_NAME,
105*4882a593Smuzhiyun .desc = DRIVER_DESC,
106*4882a593Smuzhiyun .date = "20161109",
107*4882a593Smuzhiyun .major = 1,
108*4882a593Smuzhiyun .minor = 0,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
meson_vpu_has_available_connectors(struct device * dev)111*4882a593Smuzhiyun static bool meson_vpu_has_available_connectors(struct device *dev)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct device_node *ep, *remote;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Parses each endpoint and check if remote exists */
116*4882a593Smuzhiyun for_each_endpoint_of_node(dev->of_node, ep) {
117*4882a593Smuzhiyun /* If the endpoint node exists, consider it enabled */
118*4882a593Smuzhiyun remote = of_graph_get_remote_port(ep);
119*4882a593Smuzhiyun if (remote) {
120*4882a593Smuzhiyun of_node_put(remote);
121*4882a593Smuzhiyun of_node_put(ep);
122*4882a593Smuzhiyun return true;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return false;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct regmap_config meson_regmap_config = {
130*4882a593Smuzhiyun .reg_bits = 32,
131*4882a593Smuzhiyun .val_bits = 32,
132*4882a593Smuzhiyun .reg_stride = 4,
133*4882a593Smuzhiyun .max_register = 0x1000,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
meson_vpu_init(struct meson_drm * priv)136*4882a593Smuzhiyun static void meson_vpu_init(struct meson_drm *priv)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun u32 value;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * Slave dc0 and dc5 connected to master port 1.
142*4882a593Smuzhiyun * By default other slaves are connected to master port 0.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
145*4882a593Smuzhiyun VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
146*4882a593Smuzhiyun writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* Slave dc0 connected to master port 1 */
149*4882a593Smuzhiyun value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
150*4882a593Smuzhiyun writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* Slave dc4 and dc7 connected to master port 1 */
153*4882a593Smuzhiyun value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
154*4882a593Smuzhiyun VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
155*4882a593Smuzhiyun writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Slave dc1 connected to master port 1 */
158*4882a593Smuzhiyun value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
159*4882a593Smuzhiyun writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
meson_remove_framebuffers(void)162*4882a593Smuzhiyun static void meson_remove_framebuffers(void)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun struct apertures_struct *ap;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun ap = alloc_apertures(1);
167*4882a593Smuzhiyun if (!ap)
168*4882a593Smuzhiyun return;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* The framebuffer can be located anywhere in RAM */
171*4882a593Smuzhiyun ap->ranges[0].base = 0;
172*4882a593Smuzhiyun ap->ranges[0].size = ~0;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb",
175*4882a593Smuzhiyun false);
176*4882a593Smuzhiyun kfree(ap);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun struct meson_drm_soc_attr {
180*4882a593Smuzhiyun struct meson_drm_soc_limits limits;
181*4882a593Smuzhiyun const struct soc_device_attribute *attrs;
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
185*4882a593Smuzhiyun /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun .limits = {
188*4882a593Smuzhiyun .max_hdmi_phy_freq = 1650000,
189*4882a593Smuzhiyun },
190*4882a593Smuzhiyun .attrs = (const struct soc_device_attribute []) {
191*4882a593Smuzhiyun { .soc_id = "GXL (S805*)", },
192*4882a593Smuzhiyun { /* sentinel */ },
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun },
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
meson_drv_bind_master(struct device * dev,bool has_components)197*4882a593Smuzhiyun static int meson_drv_bind_master(struct device *dev, bool has_components)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(dev);
200*4882a593Smuzhiyun const struct meson_drm_match_data *match;
201*4882a593Smuzhiyun struct meson_drm *priv;
202*4882a593Smuzhiyun struct drm_device *drm;
203*4882a593Smuzhiyun struct resource *res;
204*4882a593Smuzhiyun void __iomem *regs;
205*4882a593Smuzhiyun int ret, i;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Checks if an output connector is available */
208*4882a593Smuzhiyun if (!meson_vpu_has_available_connectors(dev)) {
209*4882a593Smuzhiyun dev_err(dev, "No output connector available\n");
210*4882a593Smuzhiyun return -ENODEV;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun match = of_device_get_match_data(dev);
214*4882a593Smuzhiyun if (!match)
215*4882a593Smuzhiyun return -ENODEV;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun drm = drm_dev_alloc(&meson_driver, dev);
218*4882a593Smuzhiyun if (IS_ERR(drm))
219*4882a593Smuzhiyun return PTR_ERR(drm);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
222*4882a593Smuzhiyun if (!priv) {
223*4882a593Smuzhiyun ret = -ENOMEM;
224*4882a593Smuzhiyun goto free_drm;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun drm->dev_private = priv;
227*4882a593Smuzhiyun priv->drm = drm;
228*4882a593Smuzhiyun priv->dev = dev;
229*4882a593Smuzhiyun priv->compat = match->compat;
230*4882a593Smuzhiyun priv->afbcd.ops = match->afbcd_ops;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
233*4882a593Smuzhiyun regs = devm_ioremap_resource(dev, res);
234*4882a593Smuzhiyun if (IS_ERR(regs)) {
235*4882a593Smuzhiyun ret = PTR_ERR(regs);
236*4882a593Smuzhiyun goto free_drm;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun priv->io_base = regs;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
242*4882a593Smuzhiyun if (!res) {
243*4882a593Smuzhiyun ret = -EINVAL;
244*4882a593Smuzhiyun goto free_drm;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun /* Simply ioremap since it may be a shared register zone */
247*4882a593Smuzhiyun regs = devm_ioremap(dev, res->start, resource_size(res));
248*4882a593Smuzhiyun if (!regs) {
249*4882a593Smuzhiyun ret = -EADDRNOTAVAIL;
250*4882a593Smuzhiyun goto free_drm;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun priv->hhi = devm_regmap_init_mmio(dev, regs,
254*4882a593Smuzhiyun &meson_regmap_config);
255*4882a593Smuzhiyun if (IS_ERR(priv->hhi)) {
256*4882a593Smuzhiyun dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
257*4882a593Smuzhiyun ret = PTR_ERR(priv->hhi);
258*4882a593Smuzhiyun goto free_drm;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun priv->canvas = meson_canvas_get(dev);
262*4882a593Smuzhiyun if (IS_ERR(priv->canvas)) {
263*4882a593Smuzhiyun ret = PTR_ERR(priv->canvas);
264*4882a593Smuzhiyun goto free_drm;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
268*4882a593Smuzhiyun if (ret)
269*4882a593Smuzhiyun goto free_drm;
270*4882a593Smuzhiyun ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
271*4882a593Smuzhiyun if (ret) {
272*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
273*4882a593Smuzhiyun goto free_drm;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
276*4882a593Smuzhiyun if (ret) {
277*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
278*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
279*4882a593Smuzhiyun goto free_drm;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
282*4882a593Smuzhiyun if (ret) {
283*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
284*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
285*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
286*4882a593Smuzhiyun goto free_drm;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun priv->vsync_irq = platform_get_irq(pdev, 0);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun ret = drm_vblank_init(drm, 1);
292*4882a593Smuzhiyun if (ret)
293*4882a593Smuzhiyun goto free_drm;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* Assign limits per soc revision/package */
296*4882a593Smuzhiyun for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
297*4882a593Smuzhiyun if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
298*4882a593Smuzhiyun priv->limits = &meson_drm_soc_attrs[i].limits;
299*4882a593Smuzhiyun break;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* Remove early framebuffers (ie. simplefb) */
304*4882a593Smuzhiyun meson_remove_framebuffers();
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun ret = drmm_mode_config_init(drm);
307*4882a593Smuzhiyun if (ret)
308*4882a593Smuzhiyun goto free_drm;
309*4882a593Smuzhiyun drm->mode_config.max_width = 3840;
310*4882a593Smuzhiyun drm->mode_config.max_height = 2160;
311*4882a593Smuzhiyun drm->mode_config.funcs = &meson_mode_config_funcs;
312*4882a593Smuzhiyun drm->mode_config.helper_private = &meson_mode_config_helpers;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* Hardware Initialization */
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun meson_vpu_init(priv);
317*4882a593Smuzhiyun meson_venc_init(priv);
318*4882a593Smuzhiyun meson_vpp_init(priv);
319*4882a593Smuzhiyun meson_viu_init(priv);
320*4882a593Smuzhiyun if (priv->afbcd.ops) {
321*4882a593Smuzhiyun ret = priv->afbcd.ops->init(priv);
322*4882a593Smuzhiyun if (ret)
323*4882a593Smuzhiyun return ret;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* Encoder Initialization */
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun ret = meson_venc_cvbs_create(priv);
329*4882a593Smuzhiyun if (ret)
330*4882a593Smuzhiyun goto free_drm;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun if (has_components) {
333*4882a593Smuzhiyun ret = component_bind_all(drm->dev, drm);
334*4882a593Smuzhiyun if (ret) {
335*4882a593Smuzhiyun dev_err(drm->dev, "Couldn't bind all components\n");
336*4882a593Smuzhiyun goto free_drm;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun ret = meson_plane_create(priv);
341*4882a593Smuzhiyun if (ret)
342*4882a593Smuzhiyun goto free_drm;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun ret = meson_overlay_create(priv);
345*4882a593Smuzhiyun if (ret)
346*4882a593Smuzhiyun goto free_drm;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun ret = meson_crtc_create(priv);
349*4882a593Smuzhiyun if (ret)
350*4882a593Smuzhiyun goto free_drm;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun ret = drm_irq_install(drm, priv->vsync_irq);
353*4882a593Smuzhiyun if (ret)
354*4882a593Smuzhiyun goto free_drm;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun drm_mode_config_reset(drm);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun drm_kms_helper_poll_init(drm);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun ret = drm_dev_register(drm, 0);
363*4882a593Smuzhiyun if (ret)
364*4882a593Smuzhiyun goto uninstall_irq;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun drm_fbdev_generic_setup(drm, 32);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun return 0;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun uninstall_irq:
371*4882a593Smuzhiyun drm_irq_uninstall(drm);
372*4882a593Smuzhiyun free_drm:
373*4882a593Smuzhiyun drm_dev_put(drm);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun return ret;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
meson_drv_bind(struct device * dev)378*4882a593Smuzhiyun static int meson_drv_bind(struct device *dev)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun return meson_drv_bind_master(dev, true);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
meson_drv_unbind(struct device * dev)383*4882a593Smuzhiyun static void meson_drv_unbind(struct device *dev)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun struct meson_drm *priv = dev_get_drvdata(dev);
386*4882a593Smuzhiyun struct drm_device *drm = priv->drm;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (priv->canvas) {
389*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
390*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
391*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
392*4882a593Smuzhiyun meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun drm_dev_unregister(drm);
396*4882a593Smuzhiyun drm_kms_helper_poll_fini(drm);
397*4882a593Smuzhiyun drm_atomic_helper_shutdown(drm);
398*4882a593Smuzhiyun component_unbind_all(dev, drm);
399*4882a593Smuzhiyun drm_irq_uninstall(drm);
400*4882a593Smuzhiyun drm_dev_put(drm);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (priv->afbcd.ops)
403*4882a593Smuzhiyun priv->afbcd.ops->exit(priv);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun static const struct component_master_ops meson_drv_master_ops = {
407*4882a593Smuzhiyun .bind = meson_drv_bind,
408*4882a593Smuzhiyun .unbind = meson_drv_unbind,
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun
meson_drv_pm_suspend(struct device * dev)411*4882a593Smuzhiyun static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun struct meson_drm *priv = dev_get_drvdata(dev);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun if (!priv)
416*4882a593Smuzhiyun return 0;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun return drm_mode_config_helper_suspend(priv->drm);
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
meson_drv_pm_resume(struct device * dev)421*4882a593Smuzhiyun static int __maybe_unused meson_drv_pm_resume(struct device *dev)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun struct meson_drm *priv = dev_get_drvdata(dev);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (!priv)
426*4882a593Smuzhiyun return 0;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun meson_vpu_init(priv);
429*4882a593Smuzhiyun meson_venc_init(priv);
430*4882a593Smuzhiyun meson_vpp_init(priv);
431*4882a593Smuzhiyun meson_viu_init(priv);
432*4882a593Smuzhiyun if (priv->afbcd.ops)
433*4882a593Smuzhiyun priv->afbcd.ops->init(priv);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return drm_mode_config_helper_resume(priv->drm);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
compare_of(struct device * dev,void * data)438*4882a593Smuzhiyun static int compare_of(struct device *dev, void *data)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
441*4882a593Smuzhiyun dev->of_node, data);
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun return dev->of_node == data;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /* Possible connectors nodes to ignore */
447*4882a593Smuzhiyun static const struct of_device_id connectors_match[] = {
448*4882a593Smuzhiyun { .compatible = "composite-video-connector" },
449*4882a593Smuzhiyun { .compatible = "svideo-connector" },
450*4882a593Smuzhiyun { .compatible = "hdmi-connector" },
451*4882a593Smuzhiyun { .compatible = "dvi-connector" },
452*4882a593Smuzhiyun {}
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun
meson_probe_remote(struct platform_device * pdev,struct component_match ** match,struct device_node * parent,struct device_node * remote)455*4882a593Smuzhiyun static int meson_probe_remote(struct platform_device *pdev,
456*4882a593Smuzhiyun struct component_match **match,
457*4882a593Smuzhiyun struct device_node *parent,
458*4882a593Smuzhiyun struct device_node *remote)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun struct device_node *ep, *remote_node;
461*4882a593Smuzhiyun int count = 1;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun /* If node is a connector, return and do not add to match table */
464*4882a593Smuzhiyun if (of_match_node(connectors_match, remote))
465*4882a593Smuzhiyun return 1;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun component_match_add(&pdev->dev, match, compare_of, remote);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun for_each_endpoint_of_node(remote, ep) {
470*4882a593Smuzhiyun remote_node = of_graph_get_remote_port_parent(ep);
471*4882a593Smuzhiyun if (!remote_node ||
472*4882a593Smuzhiyun remote_node == parent || /* Ignore parent endpoint */
473*4882a593Smuzhiyun !of_device_is_available(remote_node)) {
474*4882a593Smuzhiyun of_node_put(remote_node);
475*4882a593Smuzhiyun continue;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun count += meson_probe_remote(pdev, match, remote, remote_node);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun of_node_put(remote_node);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun return count;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
meson_drv_shutdown(struct platform_device * pdev)486*4882a593Smuzhiyun static void meson_drv_shutdown(struct platform_device *pdev)
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (!priv)
491*4882a593Smuzhiyun return;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun drm_kms_helper_poll_fini(priv->drm);
494*4882a593Smuzhiyun drm_atomic_helper_shutdown(priv->drm);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
meson_drv_probe(struct platform_device * pdev)497*4882a593Smuzhiyun static int meson_drv_probe(struct platform_device *pdev)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun struct component_match *match = NULL;
500*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
501*4882a593Smuzhiyun struct device_node *ep, *remote;
502*4882a593Smuzhiyun int count = 0;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun for_each_endpoint_of_node(np, ep) {
505*4882a593Smuzhiyun remote = of_graph_get_remote_port_parent(ep);
506*4882a593Smuzhiyun if (!remote || !of_device_is_available(remote)) {
507*4882a593Smuzhiyun of_node_put(remote);
508*4882a593Smuzhiyun continue;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun count += meson_probe_remote(pdev, &match, np, remote);
512*4882a593Smuzhiyun of_node_put(remote);
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (count && !match)
516*4882a593Smuzhiyun return meson_drv_bind_master(&pdev->dev, false);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /* If some endpoints were found, initialize the nodes */
519*4882a593Smuzhiyun if (count) {
520*4882a593Smuzhiyun dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun return component_master_add_with_match(&pdev->dev,
523*4882a593Smuzhiyun &meson_drv_master_ops,
524*4882a593Smuzhiyun match);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /* If no output endpoints were available, simply bail out */
528*4882a593Smuzhiyun return 0;
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun
meson_drv_remove(struct platform_device * pdev)531*4882a593Smuzhiyun static int meson_drv_remove(struct platform_device *pdev)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun component_master_del(&pdev->dev, &meson_drv_master_ops);
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun return 0;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun static struct meson_drm_match_data meson_drm_gxbb_data = {
539*4882a593Smuzhiyun .compat = VPU_COMPATIBLE_GXBB,
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun static struct meson_drm_match_data meson_drm_gxl_data = {
543*4882a593Smuzhiyun .compat = VPU_COMPATIBLE_GXL,
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static struct meson_drm_match_data meson_drm_gxm_data = {
547*4882a593Smuzhiyun .compat = VPU_COMPATIBLE_GXM,
548*4882a593Smuzhiyun .afbcd_ops = &meson_afbcd_gxm_ops,
549*4882a593Smuzhiyun };
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun static struct meson_drm_match_data meson_drm_g12a_data = {
552*4882a593Smuzhiyun .compat = VPU_COMPATIBLE_G12A,
553*4882a593Smuzhiyun .afbcd_ops = &meson_afbcd_g12a_ops,
554*4882a593Smuzhiyun };
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun static const struct of_device_id dt_match[] = {
557*4882a593Smuzhiyun { .compatible = "amlogic,meson-gxbb-vpu",
558*4882a593Smuzhiyun .data = (void *)&meson_drm_gxbb_data },
559*4882a593Smuzhiyun { .compatible = "amlogic,meson-gxl-vpu",
560*4882a593Smuzhiyun .data = (void *)&meson_drm_gxl_data },
561*4882a593Smuzhiyun { .compatible = "amlogic,meson-gxm-vpu",
562*4882a593Smuzhiyun .data = (void *)&meson_drm_gxm_data },
563*4882a593Smuzhiyun { .compatible = "amlogic,meson-g12a-vpu",
564*4882a593Smuzhiyun .data = (void *)&meson_drm_g12a_data },
565*4882a593Smuzhiyun {}
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, dt_match);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun static const struct dev_pm_ops meson_drv_pm_ops = {
570*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun static struct platform_driver meson_drm_platform_driver = {
574*4882a593Smuzhiyun .probe = meson_drv_probe,
575*4882a593Smuzhiyun .remove = meson_drv_remove,
576*4882a593Smuzhiyun .shutdown = meson_drv_shutdown,
577*4882a593Smuzhiyun .driver = {
578*4882a593Smuzhiyun .name = "meson-drm",
579*4882a593Smuzhiyun .of_match_table = dt_match,
580*4882a593Smuzhiyun .pm = &meson_drv_pm_ops,
581*4882a593Smuzhiyun },
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun module_platform_driver(meson_drm_platform_driver);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
587*4882a593Smuzhiyun MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
588*4882a593Smuzhiyun MODULE_DESCRIPTION(DRIVER_DESC);
589*4882a593Smuzhiyun MODULE_LICENSE("GPL");
590