1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Jitao Shi <jitao.shi@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MTK_MIPI_TX_H 8*4882a593Smuzhiyun #define _MTK_MIPI_TX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/clk.h> 11*4882a593Smuzhiyun #include <linux/clk-provider.h> 12*4882a593Smuzhiyun #include <linux/delay.h> 13*4882a593Smuzhiyun #include <linux/io.h> 14*4882a593Smuzhiyun #include <linux/module.h> 15*4882a593Smuzhiyun #include <linux/nvmem-consumer.h> 16*4882a593Smuzhiyun #include <linux/of_device.h> 17*4882a593Smuzhiyun #include <linux/platform_device.h> 18*4882a593Smuzhiyun #include <linux/phy/phy.h> 19*4882a593Smuzhiyun #include <linux/slab.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct mtk_mipitx_data { 22*4882a593Smuzhiyun const u32 mppll_preserve; 23*4882a593Smuzhiyun const struct clk_ops *mipi_tx_clk_ops; 24*4882a593Smuzhiyun void (*mipi_tx_enable_signal)(struct phy *phy); 25*4882a593Smuzhiyun void (*mipi_tx_disable_signal)(struct phy *phy); 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct mtk_mipi_tx { 29*4882a593Smuzhiyun struct device *dev; 30*4882a593Smuzhiyun void __iomem *regs; 31*4882a593Smuzhiyun u32 data_rate; 32*4882a593Smuzhiyun u32 mipitx_drive; 33*4882a593Smuzhiyun u32 rt_code[5]; 34*4882a593Smuzhiyun const struct mtk_mipitx_data *driver_data; 35*4882a593Smuzhiyun struct clk_hw pll_hw; 36*4882a593Smuzhiyun struct clk *pll; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw); 40*4882a593Smuzhiyun void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); 41*4882a593Smuzhiyun void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); 42*4882a593Smuzhiyun void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask, 43*4882a593Smuzhiyun u32 data); 44*4882a593Smuzhiyun int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, 45*4882a593Smuzhiyun unsigned long parent_rate); 46*4882a593Smuzhiyun unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, 47*4882a593Smuzhiyun unsigned long parent_rate); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun extern const struct mtk_mipitx_data mt2701_mipitx_data; 50*4882a593Smuzhiyun extern const struct mtk_mipitx_data mt8173_mipitx_data; 51*4882a593Smuzhiyun extern const struct mtk_mipitx_data mt8183_mipitx_data; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54