1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org> 4*4882a593Smuzhiyun * Parts of this file were based on the MCDE driver by Marcus Lorentzon 5*4882a593Smuzhiyun * (C) ST-Ericsson SA 2013 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MCDE_DRM_H_ 10*4882a593Smuzhiyun #define _MCDE_DRM_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Shared basic registers */ 13*4882a593Smuzhiyun #define MCDE_CR 0x00000000 14*4882a593Smuzhiyun #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0 15*4882a593Smuzhiyun #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F 16*4882a593Smuzhiyun #define MCDE_CR_IFIFOCTRLEN BIT(15) 17*4882a593Smuzhiyun #define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16) 18*4882a593Smuzhiyun #define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17) 19*4882a593Smuzhiyun #define MCDE_CR_AUTOCLKG_EN BIT(30) 20*4882a593Smuzhiyun #define MCDE_CR_MCDEEN BIT(31) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MCDE_CONF0 0x00000004 23*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX0 BIT(0) 24*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX1 BIT(1) 25*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX2 BIT(2) 26*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX3 BIT(3) 27*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX4 BIT(4) 28*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX5 BIT(5) 29*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX6 BIT(6) 30*4882a593Smuzhiyun #define MCDE_CONF0_SYNCMUX7 BIT(7) 31*4882a593Smuzhiyun #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 32*4882a593Smuzhiyun #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000 33*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX0_SHIFT 16 34*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX0_MASK 0x00070000 35*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX1_SHIFT 19 36*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX1_MASK 0x00380000 37*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX2_SHIFT 22 38*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000 39*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX3_SHIFT 25 40*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000 41*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX4_SHIFT 28 42*4882a593Smuzhiyun #define MCDE_CONF0_OUTMUX4_MASK 0x70000000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MCDE_SSP 0x00000008 45*4882a593Smuzhiyun #define MCDE_AIS 0x00000100 46*4882a593Smuzhiyun #define MCDE_IMSCERR 0x00000110 47*4882a593Smuzhiyun #define MCDE_RISERR 0x00000120 48*4882a593Smuzhiyun #define MCDE_MISERR 0x00000130 49*4882a593Smuzhiyun #define MCDE_SISERR 0x00000140 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum mcde_flow_mode { 52*4882a593Smuzhiyun /* One-shot mode: flow stops after one frame */ 53*4882a593Smuzhiyun MCDE_COMMAND_ONESHOT_FLOW, 54*4882a593Smuzhiyun /* Command mode with tearing effect (TE) IRQ sync */ 55*4882a593Smuzhiyun MCDE_COMMAND_TE_FLOW, 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Command mode with bus turn-around (BTA) and tearing effect 58*4882a593Smuzhiyun * (TE) IRQ sync. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun MCDE_COMMAND_BTA_TE_FLOW, 61*4882a593Smuzhiyun /* Video mode with tearing effect (TE) sync IRQ */ 62*4882a593Smuzhiyun MCDE_VIDEO_TE_FLOW, 63*4882a593Smuzhiyun /* Video mode with the formatter itself as sync source */ 64*4882a593Smuzhiyun MCDE_VIDEO_FORMATTER_FLOW, 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct mcde { 68*4882a593Smuzhiyun struct drm_device drm; 69*4882a593Smuzhiyun struct device *dev; 70*4882a593Smuzhiyun struct drm_panel *panel; 71*4882a593Smuzhiyun struct drm_bridge *bridge; 72*4882a593Smuzhiyun struct drm_connector *connector; 73*4882a593Smuzhiyun struct drm_simple_display_pipe pipe; 74*4882a593Smuzhiyun struct mipi_dsi_device *mdsi; 75*4882a593Smuzhiyun s16 stride; 76*4882a593Smuzhiyun enum mcde_flow_mode flow_mode; 77*4882a593Smuzhiyun unsigned int flow_active; 78*4882a593Smuzhiyun spinlock_t flow_lock; /* Locks the channel flow control */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun void __iomem *regs; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct clk *mcde_clk; 83*4882a593Smuzhiyun struct clk *lcd_clk; 84*4882a593Smuzhiyun struct clk *hdmi_clk; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct regulator *epod; 87*4882a593Smuzhiyun struct regulator *vana; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define to_mcde(dev) container_of(dev, struct mcde, drm) 91*4882a593Smuzhiyun mcde_flow_is_video(struct mcde * mcde)92*4882a593Smuzhiyunstatic inline bool mcde_flow_is_video(struct mcde *mcde) 93*4882a593Smuzhiyun { 94*4882a593Smuzhiyun return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW || 95*4882a593Smuzhiyun mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW); 96*4882a593Smuzhiyun } 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun bool mcde_dsi_irq(struct mipi_dsi_device *mdsi); 99*4882a593Smuzhiyun void mcde_dsi_te_request(struct mipi_dsi_device *mdsi); 100*4882a593Smuzhiyun void mcde_dsi_enable(struct drm_bridge *bridge); 101*4882a593Smuzhiyun void mcde_dsi_disable(struct drm_bridge *bridge); 102*4882a593Smuzhiyun extern struct platform_driver mcde_dsi_driver; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun void mcde_display_irq(struct mcde *mcde); 105*4882a593Smuzhiyun void mcde_display_disable_irqs(struct mcde *mcde); 106*4882a593Smuzhiyun int mcde_display_init(struct drm_device *drm); 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* _MCDE_DRM_H_ */ 109