xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/lima/lima_l2_cache.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/iopoll.h>
5*4882a593Smuzhiyun #include <linux/device.h>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "lima_device.h"
8*4882a593Smuzhiyun #include "lima_l2_cache.h"
9*4882a593Smuzhiyun #include "lima_regs.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define l2_cache_write(reg, data) writel(data, ip->iomem + reg)
12*4882a593Smuzhiyun #define l2_cache_read(reg) readl(ip->iomem + reg)
13*4882a593Smuzhiyun 
lima_l2_cache_wait_idle(struct lima_ip * ip)14*4882a593Smuzhiyun static int lima_l2_cache_wait_idle(struct lima_ip *ip)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun 	struct lima_device *dev = ip->dev;
17*4882a593Smuzhiyun 	int err;
18*4882a593Smuzhiyun 	u32 v;
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	err = readl_poll_timeout(ip->iomem + LIMA_L2_CACHE_STATUS, v,
21*4882a593Smuzhiyun 				 !(v & LIMA_L2_CACHE_STATUS_COMMAND_BUSY),
22*4882a593Smuzhiyun 				 0, 1000);
23*4882a593Smuzhiyun 	if (err) {
24*4882a593Smuzhiyun 		dev_err(dev->dev, "l2 cache wait command timeout\n");
25*4882a593Smuzhiyun 		return err;
26*4882a593Smuzhiyun 	}
27*4882a593Smuzhiyun 	return 0;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun 
lima_l2_cache_flush(struct lima_ip * ip)30*4882a593Smuzhiyun int lima_l2_cache_flush(struct lima_ip *ip)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun 	int ret;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	spin_lock(&ip->data.lock);
35*4882a593Smuzhiyun 	l2_cache_write(LIMA_L2_CACHE_COMMAND, LIMA_L2_CACHE_COMMAND_CLEAR_ALL);
36*4882a593Smuzhiyun 	ret = lima_l2_cache_wait_idle(ip);
37*4882a593Smuzhiyun 	spin_unlock(&ip->data.lock);
38*4882a593Smuzhiyun 	return ret;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun 
lima_l2_cache_hw_init(struct lima_ip * ip)41*4882a593Smuzhiyun static int lima_l2_cache_hw_init(struct lima_ip *ip)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	int err;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	err = lima_l2_cache_flush(ip);
46*4882a593Smuzhiyun 	if (err)
47*4882a593Smuzhiyun 		return err;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	l2_cache_write(LIMA_L2_CACHE_ENABLE,
50*4882a593Smuzhiyun 		       LIMA_L2_CACHE_ENABLE_ACCESS |
51*4882a593Smuzhiyun 		       LIMA_L2_CACHE_ENABLE_READ_ALLOCATE);
52*4882a593Smuzhiyun 	l2_cache_write(LIMA_L2_CACHE_MAX_READS, 0x1c);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
lima_l2_cache_resume(struct lima_ip * ip)57*4882a593Smuzhiyun int lima_l2_cache_resume(struct lima_ip *ip)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	return lima_l2_cache_hw_init(ip);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
lima_l2_cache_suspend(struct lima_ip * ip)62*4882a593Smuzhiyun void lima_l2_cache_suspend(struct lima_ip *ip)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
lima_l2_cache_init(struct lima_ip * ip)67*4882a593Smuzhiyun int lima_l2_cache_init(struct lima_ip *ip)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	int i;
70*4882a593Smuzhiyun 	u32 size;
71*4882a593Smuzhiyun 	struct lima_device *dev = ip->dev;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* l2_cache2 only exists when one of PP4-7 present */
74*4882a593Smuzhiyun 	if (ip->id == lima_ip_l2_cache2) {
75*4882a593Smuzhiyun 		for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
76*4882a593Smuzhiyun 			if (dev->ip[i].present)
77*4882a593Smuzhiyun 				break;
78*4882a593Smuzhiyun 		}
79*4882a593Smuzhiyun 		if (i > lima_ip_pp7)
80*4882a593Smuzhiyun 			return -ENODEV;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	spin_lock_init(&ip->data.lock);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	size = l2_cache_read(LIMA_L2_CACHE_SIZE);
86*4882a593Smuzhiyun 	dev_info(dev->dev, "l2 cache %uK, %u-way, %ubyte cache line, %ubit external bus\n",
87*4882a593Smuzhiyun 		 1 << (((size >> 16) & 0xff) - 10),
88*4882a593Smuzhiyun 		 1 << ((size >> 8) & 0xff),
89*4882a593Smuzhiyun 		 1 << (size & 0xff),
90*4882a593Smuzhiyun 		 1 << ((size >> 24) & 0xff));
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	return lima_l2_cache_hw_init(ip);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
lima_l2_cache_fini(struct lima_ip * ip)95*4882a593Smuzhiyun void lima_l2_cache_fini(struct lima_ip *ip)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun }
99