1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/component.h>
8*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <video/imx-ipu-v3.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <drm/bridge/dw_hdmi.h>
17*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
18*4882a593Smuzhiyun #include <drm/drm_edid.h>
19*4882a593Smuzhiyun #include <drm/drm_encoder.h>
20*4882a593Smuzhiyun #include <drm/drm_of.h>
21*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "imx-drm.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct imx_hdmi {
26*4882a593Smuzhiyun struct device *dev;
27*4882a593Smuzhiyun struct drm_encoder encoder;
28*4882a593Smuzhiyun struct dw_hdmi *hdmi;
29*4882a593Smuzhiyun struct regmap *regmap;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
enc_to_imx_hdmi(struct drm_encoder * e)32*4882a593Smuzhiyun static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return container_of(e, struct imx_hdmi, encoder);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 45250000, {
40*4882a593Smuzhiyun { 0x01e0, 0x0000 },
41*4882a593Smuzhiyun { 0x21e1, 0x0000 },
42*4882a593Smuzhiyun { 0x41e2, 0x0000 }
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun }, {
45*4882a593Smuzhiyun 92500000, {
46*4882a593Smuzhiyun { 0x0140, 0x0005 },
47*4882a593Smuzhiyun { 0x2141, 0x0005 },
48*4882a593Smuzhiyun { 0x4142, 0x0005 },
49*4882a593Smuzhiyun },
50*4882a593Smuzhiyun }, {
51*4882a593Smuzhiyun 148500000, {
52*4882a593Smuzhiyun { 0x00a0, 0x000a },
53*4882a593Smuzhiyun { 0x20a1, 0x000a },
54*4882a593Smuzhiyun { 0x40a2, 0x000a },
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun }, {
57*4882a593Smuzhiyun 216000000, {
58*4882a593Smuzhiyun { 0x00a0, 0x000a },
59*4882a593Smuzhiyun { 0x2001, 0x000f },
60*4882a593Smuzhiyun { 0x4002, 0x000f },
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun }, {
63*4882a593Smuzhiyun ~0UL, {
64*4882a593Smuzhiyun { 0x0000, 0x0000 },
65*4882a593Smuzhiyun { 0x0000, 0x0000 },
66*4882a593Smuzhiyun { 0x0000, 0x0000 },
67*4882a593Smuzhiyun },
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
72*4882a593Smuzhiyun /* pixelclk bpp8 bpp10 bpp12 */
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 54000000, { 0x091c, 0x091c, 0x06dc },
75*4882a593Smuzhiyun }, {
76*4882a593Smuzhiyun 58400000, { 0x091c, 0x06dc, 0x06dc },
77*4882a593Smuzhiyun }, {
78*4882a593Smuzhiyun 72000000, { 0x06dc, 0x06dc, 0x091c },
79*4882a593Smuzhiyun }, {
80*4882a593Smuzhiyun 74250000, { 0x06dc, 0x0b5c, 0x091c },
81*4882a593Smuzhiyun }, {
82*4882a593Smuzhiyun 118800000, { 0x091c, 0x091c, 0x06dc },
83*4882a593Smuzhiyun }, {
84*4882a593Smuzhiyun 216000000, { 0x06dc, 0x0b5c, 0x091c },
85*4882a593Smuzhiyun }, {
86*4882a593Smuzhiyun ~0UL, { 0x0000, 0x0000, 0x0000 },
87*4882a593Smuzhiyun },
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * Resistance term 133Ohm Cfg
92*4882a593Smuzhiyun * PREEMP config 0.00
93*4882a593Smuzhiyun * TX/CK level 10
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun static const struct dw_hdmi_phy_config imx_phy_config[] = {
96*4882a593Smuzhiyun /*pixelclk symbol term vlev */
97*4882a593Smuzhiyun { 216000000, 0x800d, 0x0005, 0x01ad},
98*4882a593Smuzhiyun { ~0UL, 0x0000, 0x0000, 0x0000}
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
dw_hdmi_imx_parse_dt(struct imx_hdmi * hdmi)101*4882a593Smuzhiyun static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct device_node *np = hdmi->dev->of_node;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
106*4882a593Smuzhiyun if (IS_ERR(hdmi->regmap)) {
107*4882a593Smuzhiyun dev_err(hdmi->dev, "Unable to get gpr\n");
108*4882a593Smuzhiyun return PTR_ERR(hdmi->regmap);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
dw_hdmi_imx_encoder_enable(struct drm_encoder * encoder)114*4882a593Smuzhiyun static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
117*4882a593Smuzhiyun int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
120*4882a593Smuzhiyun IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
121*4882a593Smuzhiyun mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
dw_hdmi_imx_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)124*4882a593Smuzhiyun static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
125*4882a593Smuzhiyun struct drm_crtc_state *crtc_state,
126*4882a593Smuzhiyun struct drm_connector_state *conn_state)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
131*4882a593Smuzhiyun imx_crtc_state->di_hsync_pin = 2;
132*4882a593Smuzhiyun imx_crtc_state->di_vsync_pin = 3;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
138*4882a593Smuzhiyun .enable = dw_hdmi_imx_encoder_enable,
139*4882a593Smuzhiyun .atomic_check = dw_hdmi_imx_atomic_check,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static enum drm_mode_status
imx6q_hdmi_mode_valid(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * info,const struct drm_display_mode * mode)143*4882a593Smuzhiyun imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
144*4882a593Smuzhiyun const struct drm_display_info *info,
145*4882a593Smuzhiyun const struct drm_display_mode *mode)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun if (mode->clock < 13500)
148*4882a593Smuzhiyun return MODE_CLOCK_LOW;
149*4882a593Smuzhiyun /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
150*4882a593Smuzhiyun if (mode->clock > 216000)
151*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return MODE_OK;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static enum drm_mode_status
imx6dl_hdmi_mode_valid(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * info,const struct drm_display_mode * mode)157*4882a593Smuzhiyun imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
158*4882a593Smuzhiyun const struct drm_display_info *info,
159*4882a593Smuzhiyun const struct drm_display_mode *mode)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun if (mode->clock < 13500)
162*4882a593Smuzhiyun return MODE_CLOCK_LOW;
163*4882a593Smuzhiyun /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
164*4882a593Smuzhiyun if (mode->clock > 216000)
165*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return MODE_OK;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
171*4882a593Smuzhiyun .mpll_cfg = imx_mpll_cfg,
172*4882a593Smuzhiyun .cur_ctr = imx_cur_ctr,
173*4882a593Smuzhiyun .phy_config = imx_phy_config,
174*4882a593Smuzhiyun .mode_valid = imx6q_hdmi_mode_valid,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
178*4882a593Smuzhiyun .mpll_cfg = imx_mpll_cfg,
179*4882a593Smuzhiyun .cur_ctr = imx_cur_ctr,
180*4882a593Smuzhiyun .phy_config = imx_phy_config,
181*4882a593Smuzhiyun .mode_valid = imx6dl_hdmi_mode_valid,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
185*4882a593Smuzhiyun { .compatible = "fsl,imx6q-hdmi",
186*4882a593Smuzhiyun .data = &imx6q_hdmi_drv_data
187*4882a593Smuzhiyun }, {
188*4882a593Smuzhiyun .compatible = "fsl,imx6dl-hdmi",
189*4882a593Smuzhiyun .data = &imx6dl_hdmi_drv_data
190*4882a593Smuzhiyun },
191*4882a593Smuzhiyun {},
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
194*4882a593Smuzhiyun
dw_hdmi_imx_bind(struct device * dev,struct device * master,void * data)195*4882a593Smuzhiyun static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
196*4882a593Smuzhiyun void *data)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(dev);
199*4882a593Smuzhiyun const struct dw_hdmi_plat_data *plat_data;
200*4882a593Smuzhiyun const struct of_device_id *match;
201*4882a593Smuzhiyun struct drm_device *drm = data;
202*4882a593Smuzhiyun struct drm_encoder *encoder;
203*4882a593Smuzhiyun struct imx_hdmi *hdmi;
204*4882a593Smuzhiyun int ret;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (!pdev->dev.of_node)
207*4882a593Smuzhiyun return -ENODEV;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun hdmi = dev_get_drvdata(dev);
210*4882a593Smuzhiyun memset(hdmi, 0, sizeof(*hdmi));
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
213*4882a593Smuzhiyun plat_data = match->data;
214*4882a593Smuzhiyun hdmi->dev = &pdev->dev;
215*4882a593Smuzhiyun encoder = &hdmi->encoder;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
218*4882a593Smuzhiyun if (ret)
219*4882a593Smuzhiyun return ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun ret = dw_hdmi_imx_parse_dt(hdmi);
222*4882a593Smuzhiyun if (ret < 0)
223*4882a593Smuzhiyun return ret;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
226*4882a593Smuzhiyun drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /*
231*4882a593Smuzhiyun * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
232*4882a593Smuzhiyun * which would have called the encoder cleanup. Do it manually.
233*4882a593Smuzhiyun */
234*4882a593Smuzhiyun if (IS_ERR(hdmi->hdmi)) {
235*4882a593Smuzhiyun ret = PTR_ERR(hdmi->hdmi);
236*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
dw_hdmi_imx_unbind(struct device * dev,struct device * master,void * data)242*4882a593Smuzhiyun static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
243*4882a593Smuzhiyun void *data)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct imx_hdmi *hdmi = dev_get_drvdata(dev);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun dw_hdmi_unbind(hdmi->hdmi);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun static const struct component_ops dw_hdmi_imx_ops = {
251*4882a593Smuzhiyun .bind = dw_hdmi_imx_bind,
252*4882a593Smuzhiyun .unbind = dw_hdmi_imx_unbind,
253*4882a593Smuzhiyun };
254*4882a593Smuzhiyun
dw_hdmi_imx_probe(struct platform_device * pdev)255*4882a593Smuzhiyun static int dw_hdmi_imx_probe(struct platform_device *pdev)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun struct imx_hdmi *hdmi;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
260*4882a593Smuzhiyun if (!hdmi)
261*4882a593Smuzhiyun return -ENOMEM;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun platform_set_drvdata(pdev, hdmi);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return component_add(&pdev->dev, &dw_hdmi_imx_ops);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
dw_hdmi_imx_remove(struct platform_device * pdev)268*4882a593Smuzhiyun static int dw_hdmi_imx_remove(struct platform_device *pdev)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun component_del(&pdev->dev, &dw_hdmi_imx_ops);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun return 0;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static struct platform_driver dw_hdmi_imx_platform_driver = {
276*4882a593Smuzhiyun .probe = dw_hdmi_imx_probe,
277*4882a593Smuzhiyun .remove = dw_hdmi_imx_remove,
278*4882a593Smuzhiyun .driver = {
279*4882a593Smuzhiyun .name = "dwhdmi-imx",
280*4882a593Smuzhiyun .of_match_table = dw_hdmi_imx_dt_ids,
281*4882a593Smuzhiyun },
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun module_platform_driver(dw_hdmi_imx_platform_driver);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
287*4882a593Smuzhiyun MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
288*4882a593Smuzhiyun MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
289*4882a593Smuzhiyun MODULE_LICENSE("GPL");
290*4882a593Smuzhiyun MODULE_ALIAS("platform:dwhdmi-imx");
291