1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2019 NXP. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DCSS_KMS_H_ 7*4882a593Smuzhiyun #define _DCSS_KMS_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <drm/drm_encoder.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct dcss_plane { 12*4882a593Smuzhiyun struct drm_plane base; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun int ch_num; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct dcss_crtc { 18*4882a593Smuzhiyun struct drm_crtc base; 19*4882a593Smuzhiyun struct drm_crtc_state *state; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct dcss_plane *plane[3]; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun int irq; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun bool disable_ctxld_kick_irq; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct dcss_kms_dev { 29*4882a593Smuzhiyun struct drm_device base; 30*4882a593Smuzhiyun struct dcss_crtc crtc; 31*4882a593Smuzhiyun struct drm_encoder encoder; 32*4882a593Smuzhiyun struct drm_connector *connector; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss); 36*4882a593Smuzhiyun void dcss_kms_detach(struct dcss_kms_dev *kms); 37*4882a593Smuzhiyun int dcss_crtc_init(struct dcss_crtc *crtc, struct drm_device *drm); 38*4882a593Smuzhiyun void dcss_crtc_deinit(struct dcss_crtc *crtc, struct drm_device *drm); 39*4882a593Smuzhiyun struct dcss_plane *dcss_plane_init(struct drm_device *drm, 40*4882a593Smuzhiyun unsigned int possible_crtcs, 41*4882a593Smuzhiyun enum drm_plane_type type, 42*4882a593Smuzhiyun unsigned int zpos); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45