1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2019 NXP.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __DCSS_PRV_H__
7*4882a593Smuzhiyun #define __DCSS_PRV_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <video/videomode.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SET 0x04
14*4882a593Smuzhiyun #define CLR 0x08
15*4882a593Smuzhiyun #define TGL 0x0C
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define dcss_writel(v, c) writel((v), (c))
18*4882a593Smuzhiyun #define dcss_readl(c) readl(c)
19*4882a593Smuzhiyun #define dcss_set(v, c) writel((v), (c) + SET)
20*4882a593Smuzhiyun #define dcss_clr(v, c) writel((v), (c) + CLR)
21*4882a593Smuzhiyun #define dcss_toggle(v, c) writel((v), (c) + TGL)
22*4882a593Smuzhiyun
dcss_update(u32 v,u32 m,void __iomem * c)23*4882a593Smuzhiyun static inline void dcss_update(u32 v, u32 m, void __iomem *c)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun writel((readl(c) & ~(m)) | (v), (c));
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define DCSS_DBG_REG(reg) {.name = #reg, .ofs = reg}
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun enum {
31*4882a593Smuzhiyun DCSS_IMX8MQ = 0,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct dcss_type_data {
35*4882a593Smuzhiyun const char *name;
36*4882a593Smuzhiyun u32 blkctl_ofs;
37*4882a593Smuzhiyun u32 ctxld_ofs;
38*4882a593Smuzhiyun u32 rdsrc_ofs;
39*4882a593Smuzhiyun u32 wrscl_ofs;
40*4882a593Smuzhiyun u32 dtg_ofs;
41*4882a593Smuzhiyun u32 scaler_ofs;
42*4882a593Smuzhiyun u32 ss_ofs;
43*4882a593Smuzhiyun u32 dpr_ofs;
44*4882a593Smuzhiyun u32 dtrc_ofs;
45*4882a593Smuzhiyun u32 dec400d_ofs;
46*4882a593Smuzhiyun u32 hdr10_ofs;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct dcss_debug_reg {
50*4882a593Smuzhiyun char *name;
51*4882a593Smuzhiyun u32 ofs;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun enum dcss_ctxld_ctx_type {
55*4882a593Smuzhiyun CTX_DB,
56*4882a593Smuzhiyun CTX_SB_HP, /* high-priority */
57*4882a593Smuzhiyun CTX_SB_LP, /* low-priority */
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun struct dcss_dev {
61*4882a593Smuzhiyun struct device *dev;
62*4882a593Smuzhiyun const struct dcss_type_data *devtype;
63*4882a593Smuzhiyun struct device_node *of_port;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun u32 start_addr;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct dcss_blkctl *blkctl;
68*4882a593Smuzhiyun struct dcss_ctxld *ctxld;
69*4882a593Smuzhiyun struct dcss_dpr *dpr;
70*4882a593Smuzhiyun struct dcss_dtg *dtg;
71*4882a593Smuzhiyun struct dcss_ss *ss;
72*4882a593Smuzhiyun struct dcss_hdr10 *hdr10;
73*4882a593Smuzhiyun struct dcss_scaler *scaler;
74*4882a593Smuzhiyun struct dcss_dtrc *dtrc;
75*4882a593Smuzhiyun struct dcss_dec400d *dec400d;
76*4882a593Smuzhiyun struct dcss_wrscl *wrscl;
77*4882a593Smuzhiyun struct dcss_rdsrc *rdsrc;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct clk *apb_clk;
80*4882a593Smuzhiyun struct clk *axi_clk;
81*4882a593Smuzhiyun struct clk *pix_clk;
82*4882a593Smuzhiyun struct clk *rtrm_clk;
83*4882a593Smuzhiyun struct clk *dtrc_clk;
84*4882a593Smuzhiyun struct clk *pll_src_clk;
85*4882a593Smuzhiyun struct clk *pll_phy_ref_clk;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun bool hdmi_output;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun void (*disable_callback)(void *data);
90*4882a593Smuzhiyun struct completion disable_completion;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev);
94*4882a593Smuzhiyun struct drm_device *dcss_drv_dev_to_drm(struct device *dev);
95*4882a593Smuzhiyun struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output);
96*4882a593Smuzhiyun void dcss_dev_destroy(struct dcss_dev *dcss);
97*4882a593Smuzhiyun int dcss_dev_runtime_suspend(struct device *dev);
98*4882a593Smuzhiyun int dcss_dev_runtime_resume(struct device *dev);
99*4882a593Smuzhiyun int dcss_dev_suspend(struct device *dev);
100*4882a593Smuzhiyun int dcss_dev_resume(struct device *dev);
101*4882a593Smuzhiyun void dcss_enable_dtg_and_ss(struct dcss_dev *dcss);
102*4882a593Smuzhiyun void dcss_disable_dtg_and_ss(struct dcss_dev *dcss);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* BLKCTL */
105*4882a593Smuzhiyun int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base);
106*4882a593Smuzhiyun void dcss_blkctl_cfg(struct dcss_blkctl *blkctl);
107*4882a593Smuzhiyun void dcss_blkctl_exit(struct dcss_blkctl *blkctl);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* CTXLD */
110*4882a593Smuzhiyun int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base);
111*4882a593Smuzhiyun void dcss_ctxld_exit(struct dcss_ctxld *ctxld);
112*4882a593Smuzhiyun void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id,
113*4882a593Smuzhiyun u32 val, u32 reg_idx);
114*4882a593Smuzhiyun int dcss_ctxld_resume(struct dcss_ctxld *dcss_ctxld);
115*4882a593Smuzhiyun int dcss_ctxld_suspend(struct dcss_ctxld *dcss_ctxld);
116*4882a593Smuzhiyun void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctlxd, u32 ctx_id, u32 val,
117*4882a593Smuzhiyun u32 reg_ofs);
118*4882a593Smuzhiyun void dcss_ctxld_kick(struct dcss_ctxld *ctxld);
119*4882a593Smuzhiyun bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld);
120*4882a593Smuzhiyun int dcss_ctxld_enable(struct dcss_ctxld *ctxld);
121*4882a593Smuzhiyun void dcss_ctxld_register_completion(struct dcss_ctxld *ctxld,
122*4882a593Smuzhiyun struct completion *dis_completion);
123*4882a593Smuzhiyun void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* DPR */
126*4882a593Smuzhiyun int dcss_dpr_init(struct dcss_dev *dcss, unsigned long dpr_base);
127*4882a593Smuzhiyun void dcss_dpr_exit(struct dcss_dpr *dpr);
128*4882a593Smuzhiyun void dcss_dpr_write_sysctrl(struct dcss_dpr *dpr);
129*4882a593Smuzhiyun void dcss_dpr_set_res(struct dcss_dpr *dpr, int ch_num, u32 xres, u32 yres);
130*4882a593Smuzhiyun void dcss_dpr_addr_set(struct dcss_dpr *dpr, int ch_num, u32 luma_base_addr,
131*4882a593Smuzhiyun u32 chroma_base_addr, u16 pitch);
132*4882a593Smuzhiyun void dcss_dpr_enable(struct dcss_dpr *dpr, int ch_num, bool en);
133*4882a593Smuzhiyun void dcss_dpr_format_set(struct dcss_dpr *dpr, int ch_num,
134*4882a593Smuzhiyun const struct drm_format_info *format, u64 modifier);
135*4882a593Smuzhiyun void dcss_dpr_set_rotation(struct dcss_dpr *dpr, int ch_num, u32 rotation);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* DTG */
138*4882a593Smuzhiyun int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base);
139*4882a593Smuzhiyun void dcss_dtg_exit(struct dcss_dtg *dtg);
140*4882a593Smuzhiyun bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg);
141*4882a593Smuzhiyun void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en);
142*4882a593Smuzhiyun void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg);
143*4882a593Smuzhiyun void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm);
144*4882a593Smuzhiyun void dcss_dtg_css_set(struct dcss_dtg *dtg);
145*4882a593Smuzhiyun void dcss_dtg_enable(struct dcss_dtg *dtg);
146*4882a593Smuzhiyun void dcss_dtg_shutoff(struct dcss_dtg *dtg);
147*4882a593Smuzhiyun bool dcss_dtg_is_enabled(struct dcss_dtg *dtg);
148*4882a593Smuzhiyun void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en);
149*4882a593Smuzhiyun bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha);
150*4882a593Smuzhiyun void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,
151*4882a593Smuzhiyun const struct drm_format_info *format, int alpha);
152*4882a593Smuzhiyun void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,
153*4882a593Smuzhiyun int px, int py, int pw, int ph);
154*4882a593Smuzhiyun void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* SUBSAM */
157*4882a593Smuzhiyun int dcss_ss_init(struct dcss_dev *dcss, unsigned long subsam_base);
158*4882a593Smuzhiyun void dcss_ss_exit(struct dcss_ss *ss);
159*4882a593Smuzhiyun void dcss_ss_enable(struct dcss_ss *ss);
160*4882a593Smuzhiyun void dcss_ss_shutoff(struct dcss_ss *ss);
161*4882a593Smuzhiyun void dcss_ss_subsam_set(struct dcss_ss *ss);
162*4882a593Smuzhiyun void dcss_ss_sync_set(struct dcss_ss *ss, struct videomode *vm,
163*4882a593Smuzhiyun bool phsync, bool pvsync);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* SCALER */
166*4882a593Smuzhiyun int dcss_scaler_init(struct dcss_dev *dcss, unsigned long scaler_base);
167*4882a593Smuzhiyun void dcss_scaler_exit(struct dcss_scaler *scl);
168*4882a593Smuzhiyun void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num,
169*4882a593Smuzhiyun const struct drm_format_info *format,
170*4882a593Smuzhiyun int src_xres, int src_yres, int dst_xres, int dst_yres,
171*4882a593Smuzhiyun u32 vrefresh_hz);
172*4882a593Smuzhiyun void dcss_scaler_ch_enable(struct dcss_scaler *scl, int ch_num, bool en);
173*4882a593Smuzhiyun int dcss_scaler_get_min_max_ratios(struct dcss_scaler *scl, int ch_num,
174*4882a593Smuzhiyun int *min, int *max);
175*4882a593Smuzhiyun void dcss_scaler_write_sclctrl(struct dcss_scaler *scl);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun #endif /* __DCSS_PRV_H__ */
178