1*4882a593Smuzhiyun // SPDX-License-Identifier: MIT
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include "i915_drv.h"
7*4882a593Smuzhiyun #include "intel_memory_region.h"
8*4882a593Smuzhiyun #include "gem/i915_gem_lmem.h"
9*4882a593Smuzhiyun #include "gem/i915_gem_region.h"
10*4882a593Smuzhiyun #include "intel_region_lmem.h"
11*4882a593Smuzhiyun
init_fake_lmem_bar(struct intel_memory_region * mem)12*4882a593Smuzhiyun static int init_fake_lmem_bar(struct intel_memory_region *mem)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun struct drm_i915_private *i915 = mem->i915;
15*4882a593Smuzhiyun struct i915_ggtt *ggtt = &i915->ggtt;
16*4882a593Smuzhiyun unsigned long n;
17*4882a593Smuzhiyun int ret;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* We want to 1:1 map the mappable aperture to our reserved region */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun mem->fake_mappable.start = 0;
22*4882a593Smuzhiyun mem->fake_mappable.size = resource_size(&mem->region);
23*4882a593Smuzhiyun mem->fake_mappable.color = I915_COLOR_UNEVICTABLE;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun ret = drm_mm_reserve_node(&ggtt->vm.mm, &mem->fake_mappable);
26*4882a593Smuzhiyun if (ret)
27*4882a593Smuzhiyun return ret;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun mem->remap_addr = dma_map_resource(&i915->drm.pdev->dev,
30*4882a593Smuzhiyun mem->region.start,
31*4882a593Smuzhiyun mem->fake_mappable.size,
32*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL,
33*4882a593Smuzhiyun DMA_ATTR_FORCE_CONTIGUOUS);
34*4882a593Smuzhiyun if (dma_mapping_error(&i915->drm.pdev->dev, mem->remap_addr)) {
35*4882a593Smuzhiyun drm_mm_remove_node(&mem->fake_mappable);
36*4882a593Smuzhiyun return -EINVAL;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun for (n = 0; n < mem->fake_mappable.size >> PAGE_SHIFT; ++n) {
40*4882a593Smuzhiyun ggtt->vm.insert_page(&ggtt->vm,
41*4882a593Smuzhiyun mem->remap_addr + (n << PAGE_SHIFT),
42*4882a593Smuzhiyun n << PAGE_SHIFT,
43*4882a593Smuzhiyun I915_CACHE_NONE, 0);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun mem->region = (struct resource)DEFINE_RES_MEM(mem->remap_addr,
47*4882a593Smuzhiyun mem->fake_mappable.size);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
release_fake_lmem_bar(struct intel_memory_region * mem)52*4882a593Smuzhiyun static void release_fake_lmem_bar(struct intel_memory_region *mem)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun if (!drm_mm_node_allocated(&mem->fake_mappable))
55*4882a593Smuzhiyun return;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun drm_mm_remove_node(&mem->fake_mappable);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun dma_unmap_resource(&mem->i915->drm.pdev->dev,
60*4882a593Smuzhiyun mem->remap_addr,
61*4882a593Smuzhiyun mem->fake_mappable.size,
62*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL,
63*4882a593Smuzhiyun DMA_ATTR_FORCE_CONTIGUOUS);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static void
region_lmem_release(struct intel_memory_region * mem)67*4882a593Smuzhiyun region_lmem_release(struct intel_memory_region *mem)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun release_fake_lmem_bar(mem);
70*4882a593Smuzhiyun io_mapping_fini(&mem->iomap);
71*4882a593Smuzhiyun intel_memory_region_release_buddy(mem);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static int
region_lmem_init(struct intel_memory_region * mem)75*4882a593Smuzhiyun region_lmem_init(struct intel_memory_region *mem)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int ret;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (mem->i915->params.fake_lmem_start) {
80*4882a593Smuzhiyun ret = init_fake_lmem_bar(mem);
81*4882a593Smuzhiyun GEM_BUG_ON(ret);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (!io_mapping_init_wc(&mem->iomap,
85*4882a593Smuzhiyun mem->io_start,
86*4882a593Smuzhiyun resource_size(&mem->region)))
87*4882a593Smuzhiyun return -EIO;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun ret = intel_memory_region_init_buddy(mem);
90*4882a593Smuzhiyun if (ret)
91*4882a593Smuzhiyun io_mapping_fini(&mem->iomap);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun intel_memory_region_set_name(mem, "local");
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return ret;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun const struct intel_memory_region_ops intel_region_lmem_ops = {
99*4882a593Smuzhiyun .init = region_lmem_init,
100*4882a593Smuzhiyun .release = region_lmem_release,
101*4882a593Smuzhiyun .create_object = __i915_gem_lmem_object_create,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun struct intel_memory_region *
intel_setup_fake_lmem(struct drm_i915_private * i915)105*4882a593Smuzhiyun intel_setup_fake_lmem(struct drm_i915_private *i915)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct pci_dev *pdev = i915->drm.pdev;
108*4882a593Smuzhiyun struct intel_memory_region *mem;
109*4882a593Smuzhiyun resource_size_t mappable_end;
110*4882a593Smuzhiyun resource_size_t io_start;
111*4882a593Smuzhiyun resource_size_t start;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
114*4882a593Smuzhiyun GEM_BUG_ON(!i915->params.fake_lmem_start);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Your mappable aperture belongs to me now! */
117*4882a593Smuzhiyun mappable_end = pci_resource_len(pdev, 2);
118*4882a593Smuzhiyun io_start = pci_resource_start(pdev, 2),
119*4882a593Smuzhiyun start = i915->params.fake_lmem_start;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun mem = intel_memory_region_create(i915,
122*4882a593Smuzhiyun start,
123*4882a593Smuzhiyun mappable_end,
124*4882a593Smuzhiyun PAGE_SIZE,
125*4882a593Smuzhiyun io_start,
126*4882a593Smuzhiyun &intel_region_lmem_ops);
127*4882a593Smuzhiyun if (!IS_ERR(mem)) {
128*4882a593Smuzhiyun drm_info(&i915->drm, "Intel graphics fake LMEM: %pR\n",
129*4882a593Smuzhiyun &mem->region);
130*4882a593Smuzhiyun drm_info(&i915->drm,
131*4882a593Smuzhiyun "Intel graphics fake LMEM IO start: %llx\n",
132*4882a593Smuzhiyun (u64)mem->io_start);
133*4882a593Smuzhiyun drm_info(&i915->drm, "Intel graphics fake LMEM size: %llx\n",
134*4882a593Smuzhiyun (u64)resource_size(&mem->region));
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return mem;
138*4882a593Smuzhiyun }
139