1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __INTEL_PM_H__ 7*4882a593Smuzhiyun #define __INTEL_PM_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "display/intel_bw.h" 12*4882a593Smuzhiyun #include "display/intel_global_state.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "i915_reg.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct drm_device; 17*4882a593Smuzhiyun struct drm_i915_private; 18*4882a593Smuzhiyun struct i915_request; 19*4882a593Smuzhiyun struct intel_atomic_state; 20*4882a593Smuzhiyun struct intel_crtc; 21*4882a593Smuzhiyun struct intel_crtc_state; 22*4882a593Smuzhiyun struct intel_plane; 23*4882a593Smuzhiyun struct skl_ddb_entry; 24*4882a593Smuzhiyun struct skl_pipe_wm; 25*4882a593Smuzhiyun struct skl_wm_level; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun void intel_init_clock_gating(struct drm_i915_private *dev_priv); 28*4882a593Smuzhiyun void intel_suspend_hw(struct drm_i915_private *dev_priv); 29*4882a593Smuzhiyun int ilk_wm_max_level(const struct drm_i915_private *dev_priv); 30*4882a593Smuzhiyun void intel_update_watermarks(struct intel_crtc *crtc); 31*4882a593Smuzhiyun void intel_init_pm(struct drm_i915_private *dev_priv); 32*4882a593Smuzhiyun void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); 33*4882a593Smuzhiyun void intel_pm_setup(struct drm_i915_private *dev_priv); 34*4882a593Smuzhiyun void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); 35*4882a593Smuzhiyun void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); 36*4882a593Smuzhiyun void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); 37*4882a593Smuzhiyun void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); 38*4882a593Smuzhiyun u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv); 39*4882a593Smuzhiyun void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 40*4882a593Smuzhiyun struct skl_ddb_entry *ddb_y, 41*4882a593Smuzhiyun struct skl_ddb_entry *ddb_uv); 42*4882a593Smuzhiyun void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv); 43*4882a593Smuzhiyun u16 intel_get_ddb_size(struct drm_i915_private *dev_priv); 44*4882a593Smuzhiyun u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, 45*4882a593Smuzhiyun const struct skl_ddb_entry *entry); 46*4882a593Smuzhiyun void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 47*4882a593Smuzhiyun struct skl_pipe_wm *out); 48*4882a593Smuzhiyun void g4x_wm_sanitize(struct drm_i915_private *dev_priv); 49*4882a593Smuzhiyun void vlv_wm_sanitize(struct drm_i915_private *dev_priv); 50*4882a593Smuzhiyun bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, 51*4882a593Smuzhiyun const struct intel_bw_state *bw_state); 52*4882a593Smuzhiyun int intel_enable_sagv(struct drm_i915_private *dev_priv); 53*4882a593Smuzhiyun int intel_disable_sagv(struct drm_i915_private *dev_priv); 54*4882a593Smuzhiyun void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 55*4882a593Smuzhiyun void intel_sagv_post_plane_update(struct intel_atomic_state *state); 56*4882a593Smuzhiyun bool skl_wm_level_equals(const struct skl_wm_level *l1, 57*4882a593Smuzhiyun const struct skl_wm_level *l2); 58*4882a593Smuzhiyun bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 59*4882a593Smuzhiyun const struct skl_ddb_entry *entries, 60*4882a593Smuzhiyun int num_entries, int ignore_idx); 61*4882a593Smuzhiyun void skl_write_plane_wm(struct intel_plane *plane, 62*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 63*4882a593Smuzhiyun void skl_write_cursor_wm(struct intel_plane *plane, 64*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 65*4882a593Smuzhiyun bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv); 66*4882a593Smuzhiyun void intel_init_ipc(struct drm_i915_private *dev_priv); 67*4882a593Smuzhiyun void intel_enable_ipc(struct drm_i915_private *dev_priv); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct intel_dbuf_state { 72*4882a593Smuzhiyun struct intel_global_state base; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun u8 enabled_slices; 75*4882a593Smuzhiyun u8 active_pipes; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun int intel_dbuf_init(struct drm_i915_private *dev_priv); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct intel_dbuf_state * 81*4882a593Smuzhiyun intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) 84*4882a593Smuzhiyun #define intel_atomic_get_old_dbuf_state(state) \ 85*4882a593Smuzhiyun to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj)) 86*4882a593Smuzhiyun #define intel_atomic_get_new_dbuf_state(state) \ 87*4882a593Smuzhiyun to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj)) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun int intel_dbuf_init(struct drm_i915_private *dev_priv); 90*4882a593Smuzhiyun void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 91*4882a593Smuzhiyun void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* __INTEL_PM_H__ */ 94