1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2019 Intel Corporation. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __INTEL_PCH__ 7*4882a593Smuzhiyun #define __INTEL_PCH__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct drm_i915_private; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Sorted by south display engine compatibility. 13*4882a593Smuzhiyun * If the new PCH comes with a south display engine that is not 14*4882a593Smuzhiyun * inherited from the latest item, please do not add it to the 15*4882a593Smuzhiyun * end. Instead, add it right after its "parent" PCH. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum intel_pch { 18*4882a593Smuzhiyun PCH_NOP = -1, /* PCH without south display */ 19*4882a593Smuzhiyun PCH_NONE = 0, /* No PCH present */ 20*4882a593Smuzhiyun PCH_IBX, /* Ibexpeak PCH */ 21*4882a593Smuzhiyun PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ 22*4882a593Smuzhiyun PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ 23*4882a593Smuzhiyun PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ 24*4882a593Smuzhiyun PCH_CNP, /* Cannon/Comet Lake PCH */ 25*4882a593Smuzhiyun PCH_ICP, /* Ice Lake PCH */ 26*4882a593Smuzhiyun PCH_JSP, /* Jasper Lake PCH */ 27*4882a593Smuzhiyun PCH_MCC, /* Mule Creek Canyon PCH */ 28*4882a593Smuzhiyun PCH_TGP, /* Tiger Lake PCH */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Fake PCHs, functionality handled on the same PCI dev */ 31*4882a593Smuzhiyun PCH_DG1 = 1024, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define INTEL_PCH_DEVICE_ID_MASK 0xff80 35*4882a593Smuzhiyun #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 36*4882a593Smuzhiyun #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 37*4882a593Smuzhiyun #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 38*4882a593Smuzhiyun #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 39*4882a593Smuzhiyun #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 40*4882a593Smuzhiyun #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 41*4882a593Smuzhiyun #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 42*4882a593Smuzhiyun #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 43*4882a593Smuzhiyun #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 44*4882a593Smuzhiyun #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 45*4882a593Smuzhiyun #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 46*4882a593Smuzhiyun #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 47*4882a593Smuzhiyun #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 48*4882a593Smuzhiyun #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 49*4882a593Smuzhiyun #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 50*4882a593Smuzhiyun #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 51*4882a593Smuzhiyun #define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880 52*4882a593Smuzhiyun #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 53*4882a593Smuzhiyun #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 54*4882a593Smuzhiyun #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 55*4882a593Smuzhiyun #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 56*4882a593Smuzhiyun #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 57*4882a593Smuzhiyun #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 58*4882a593Smuzhiyun #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) 61*4882a593Smuzhiyun #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) 62*4882a593Smuzhiyun #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) 63*4882a593Smuzhiyun #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) 64*4882a593Smuzhiyun #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) 65*4882a593Smuzhiyun #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) 66*4882a593Smuzhiyun #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) 67*4882a593Smuzhiyun #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) 68*4882a593Smuzhiyun #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) 69*4882a593Smuzhiyun #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) 70*4882a593Smuzhiyun #define HAS_PCH_LPT_LP(dev_priv) \ 71*4882a593Smuzhiyun (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ 72*4882a593Smuzhiyun INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) 73*4882a593Smuzhiyun #define HAS_PCH_LPT_H(dev_priv) \ 74*4882a593Smuzhiyun (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ 75*4882a593Smuzhiyun INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) 76*4882a593Smuzhiyun #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) 77*4882a593Smuzhiyun #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) 78*4882a593Smuzhiyun #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 79*4882a593Smuzhiyun #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun void intel_detect_pch(struct drm_i915_private *dev_priv); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* __INTEL_PCH__ */ 84