1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPDX-License-Identifier: MIT
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * i915_sw_fence.h - library routines for N:M synchronisation points
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2016 Intel Corporation
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _I915_SW_FENCE_H_
10*4882a593Smuzhiyun #define _I915_SW_FENCE_H_
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/dma-fence.h>
13*4882a593Smuzhiyun #include <linux/gfp.h>
14*4882a593Smuzhiyun #include <linux/kref.h>
15*4882a593Smuzhiyun #include <linux/notifier.h> /* for NOTIFY_DONE */
16*4882a593Smuzhiyun #include <linux/wait.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct completion;
19*4882a593Smuzhiyun struct dma_resv;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct i915_sw_fence {
22*4882a593Smuzhiyun wait_queue_head_t wait;
23*4882a593Smuzhiyun unsigned long flags;
24*4882a593Smuzhiyun atomic_t pending;
25*4882a593Smuzhiyun int error;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define I915_SW_FENCE_CHECKED_BIT 0 /* used internally for DAG checking */
29*4882a593Smuzhiyun #define I915_SW_FENCE_PRIVATE_BIT 1 /* available for use by owner */
30*4882a593Smuzhiyun #define I915_SW_FENCE_MASK (~3)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun enum i915_sw_fence_notify {
33*4882a593Smuzhiyun FENCE_COMPLETE,
34*4882a593Smuzhiyun FENCE_FREE
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
38*4882a593Smuzhiyun enum i915_sw_fence_notify state);
39*4882a593Smuzhiyun #define __i915_sw_fence_call __aligned(4)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun void __i915_sw_fence_init(struct i915_sw_fence *fence,
42*4882a593Smuzhiyun i915_sw_fence_notify_t fn,
43*4882a593Smuzhiyun const char *name,
44*4882a593Smuzhiyun struct lock_class_key *key);
45*4882a593Smuzhiyun #ifdef CONFIG_LOCKDEP
46*4882a593Smuzhiyun #define i915_sw_fence_init(fence, fn) \
47*4882a593Smuzhiyun do { \
48*4882a593Smuzhiyun static struct lock_class_key __key; \
49*4882a593Smuzhiyun \
50*4882a593Smuzhiyun __i915_sw_fence_init((fence), (fn), #fence, &__key); \
51*4882a593Smuzhiyun } while (0)
52*4882a593Smuzhiyun #else
53*4882a593Smuzhiyun #define i915_sw_fence_init(fence, fn) \
54*4882a593Smuzhiyun __i915_sw_fence_init((fence), (fn), NULL, NULL)
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun void i915_sw_fence_reinit(struct i915_sw_fence *fence);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
60*4882a593Smuzhiyun void i915_sw_fence_fini(struct i915_sw_fence *fence);
61*4882a593Smuzhiyun #else
i915_sw_fence_fini(struct i915_sw_fence * fence)62*4882a593Smuzhiyun static inline void i915_sw_fence_fini(struct i915_sw_fence *fence) {}
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun void i915_sw_fence_commit(struct i915_sw_fence *fence);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun int i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence,
68*4882a593Smuzhiyun struct i915_sw_fence *after,
69*4882a593Smuzhiyun wait_queue_entry_t *wq);
70*4882a593Smuzhiyun int i915_sw_fence_await_sw_fence_gfp(struct i915_sw_fence *fence,
71*4882a593Smuzhiyun struct i915_sw_fence *after,
72*4882a593Smuzhiyun gfp_t gfp);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct i915_sw_dma_fence_cb {
75*4882a593Smuzhiyun struct dma_fence_cb base;
76*4882a593Smuzhiyun struct i915_sw_fence *fence;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
80*4882a593Smuzhiyun struct dma_fence *dma,
81*4882a593Smuzhiyun struct i915_sw_dma_fence_cb *cb);
82*4882a593Smuzhiyun int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
83*4882a593Smuzhiyun struct dma_fence *dma,
84*4882a593Smuzhiyun unsigned long timeout,
85*4882a593Smuzhiyun gfp_t gfp);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
88*4882a593Smuzhiyun struct dma_resv *resv,
89*4882a593Smuzhiyun const struct dma_fence_ops *exclude,
90*4882a593Smuzhiyun bool write,
91*4882a593Smuzhiyun unsigned long timeout,
92*4882a593Smuzhiyun gfp_t gfp);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun bool i915_sw_fence_await(struct i915_sw_fence *fence);
95*4882a593Smuzhiyun void i915_sw_fence_complete(struct i915_sw_fence *fence);
96*4882a593Smuzhiyun
i915_sw_fence_signaled(const struct i915_sw_fence * fence)97*4882a593Smuzhiyun static inline bool i915_sw_fence_signaled(const struct i915_sw_fence *fence)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun return atomic_read(&fence->pending) <= 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
i915_sw_fence_done(const struct i915_sw_fence * fence)102*4882a593Smuzhiyun static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun return atomic_read(&fence->pending) < 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
i915_sw_fence_wait(struct i915_sw_fence * fence)107*4882a593Smuzhiyun static inline void i915_sw_fence_wait(struct i915_sw_fence *fence)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun wait_event(fence->wait, i915_sw_fence_done(fence));
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static inline void
i915_sw_fence_set_error_once(struct i915_sw_fence * fence,int error)113*4882a593Smuzhiyun i915_sw_fence_set_error_once(struct i915_sw_fence *fence, int error)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun if (unlikely(error))
116*4882a593Smuzhiyun cmpxchg(&fence->error, 0, error);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #endif /* _I915_SW_FENCE_H_ */
120