1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef _I915_PVINFO_H_ 25*4882a593Smuzhiyun #define _I915_PVINFO_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <linux/types.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* The MMIO offset of the shared info between guest and host emulator */ 30*4882a593Smuzhiyun #define VGT_PVINFO_PAGE 0x78000 31*4882a593Smuzhiyun #define VGT_PVINFO_SIZE 0x1000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * The following structure pages are defined in GEN MMIO space 35*4882a593Smuzhiyun * for virtualization. (One page for now) 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ 38*4882a593Smuzhiyun #define VGT_VERSION_MAJOR 1 39*4882a593Smuzhiyun #define VGT_VERSION_MINOR 0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * notifications from guest to vgpu device model 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun enum vgt_g2v_type { 45*4882a593Smuzhiyun VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2, 46*4882a593Smuzhiyun VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY, 47*4882a593Smuzhiyun VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE, 48*4882a593Smuzhiyun VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, 49*4882a593Smuzhiyun VGT_G2V_EXECLIST_CONTEXT_CREATE, 50*4882a593Smuzhiyun VGT_G2V_EXECLIST_CONTEXT_DESTROY, 51*4882a593Smuzhiyun VGT_G2V_MAX, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * VGT capabilities type 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define VGT_CAPS_FULL_PPGTT BIT(2) 58*4882a593Smuzhiyun #define VGT_CAPS_HWSP_EMULATION BIT(3) 59*4882a593Smuzhiyun #define VGT_CAPS_HUGE_GTT BIT(4) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct vgt_if { 62*4882a593Smuzhiyun u64 magic; /* VGT_MAGIC */ 63*4882a593Smuzhiyun u16 version_major; 64*4882a593Smuzhiyun u16 version_minor; 65*4882a593Smuzhiyun u32 vgt_id; /* ID of vGT instance */ 66*4882a593Smuzhiyun u32 vgt_caps; /* VGT capabilities */ 67*4882a593Smuzhiyun u32 rsv1[11]; /* pad to offset 0x40 */ 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * Data structure to describe the balooning info of resources. 70*4882a593Smuzhiyun * Each VM can only have one portion of continuous area for now. 71*4882a593Smuzhiyun * (May support scattered resource in future) 72*4882a593Smuzhiyun * (starting from offset 0x40) 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun struct { 75*4882a593Smuzhiyun /* Aperture register balooning */ 76*4882a593Smuzhiyun struct { 77*4882a593Smuzhiyun u32 base; 78*4882a593Smuzhiyun u32 size; 79*4882a593Smuzhiyun } mappable_gmadr; /* aperture */ 80*4882a593Smuzhiyun /* GMADR register balooning */ 81*4882a593Smuzhiyun struct { 82*4882a593Smuzhiyun u32 base; 83*4882a593Smuzhiyun u32 size; 84*4882a593Smuzhiyun } nonmappable_gmadr; /* non aperture */ 85*4882a593Smuzhiyun /* allowed fence registers */ 86*4882a593Smuzhiyun u32 fence_num; 87*4882a593Smuzhiyun u32 rsv2[3]; 88*4882a593Smuzhiyun } avail_rs; /* available/assigned resource */ 89*4882a593Smuzhiyun u32 rsv3[0x200 - 24]; /* pad to half page */ 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * The bottom half page is for response from Gfx driver to hypervisor. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun u32 rsv4; 94*4882a593Smuzhiyun u32 display_ready; /* ready for display owner switch */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun u32 rsv5[4]; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun u32 g2v_notify; 99*4882a593Smuzhiyun u32 rsv6[5]; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun u32 cursor_x_hot; 102*4882a593Smuzhiyun u32 cursor_y_hot; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct { 105*4882a593Smuzhiyun u32 lo; 106*4882a593Smuzhiyun u32 hi; 107*4882a593Smuzhiyun } pdp[4]; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun u32 execlist_context_descriptor_lo; 110*4882a593Smuzhiyun u32 execlist_context_descriptor_hi; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun u32 rsv7[0x200 - 24]; /* pad to one page */ 113*4882a593Smuzhiyun } __packed; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define vgtif_offset(x) (offsetof(struct vgt_if, x)) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x)) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* vGPU display status to be used by the host side */ 120*4882a593Smuzhiyun #define VGT_DRV_DISPLAY_NOT_READY 0 121*4882a593Smuzhiyun #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* _I915_PVINFO_H_ */ 124