1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __I915_IRQ_H__
7*4882a593Smuzhiyun #define __I915_IRQ_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/ktime.h>
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "display/intel_display.h"
13*4882a593Smuzhiyun #include "i915_reg.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct drm_crtc;
16*4882a593Smuzhiyun struct drm_device;
17*4882a593Smuzhiyun struct drm_display_mode;
18*4882a593Smuzhiyun struct drm_i915_private;
19*4882a593Smuzhiyun struct intel_crtc;
20*4882a593Smuzhiyun struct intel_uncore;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun void intel_irq_init(struct drm_i915_private *dev_priv);
23*4882a593Smuzhiyun void intel_irq_fini(struct drm_i915_private *dev_priv);
24*4882a593Smuzhiyun int intel_irq_install(struct drm_i915_private *dev_priv);
25*4882a593Smuzhiyun void intel_irq_uninstall(struct drm_i915_private *dev_priv);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
28*4882a593Smuzhiyun enum pipe pipe);
29*4882a593Smuzhiyun void
30*4882a593Smuzhiyun i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
31*4882a593Smuzhiyun u32 status_mask);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun void
34*4882a593Smuzhiyun i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
35*4882a593Smuzhiyun u32 status_mask);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
38*4882a593Smuzhiyun void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
41*4882a593Smuzhiyun u32 mask,
42*4882a593Smuzhiyun u32 bits);
43*4882a593Smuzhiyun void ilk_update_display_irq(struct drm_i915_private *dev_priv,
44*4882a593Smuzhiyun u32 interrupt_mask,
45*4882a593Smuzhiyun u32 enabled_irq_mask);
46*4882a593Smuzhiyun static inline void
ilk_enable_display_irq(struct drm_i915_private * dev_priv,u32 bits)47*4882a593Smuzhiyun ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun ilk_update_display_irq(dev_priv, bits, bits);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun static inline void
ilk_disable_display_irq(struct drm_i915_private * dev_priv,u32 bits)52*4882a593Smuzhiyun ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun ilk_update_display_irq(dev_priv, bits, 0);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
57*4882a593Smuzhiyun enum pipe pipe,
58*4882a593Smuzhiyun u32 interrupt_mask,
59*4882a593Smuzhiyun u32 enabled_irq_mask);
bdw_enable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,u32 bits)60*4882a593Smuzhiyun static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
61*4882a593Smuzhiyun enum pipe pipe, u32 bits)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
64*4882a593Smuzhiyun }
bdw_disable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,u32 bits)65*4882a593Smuzhiyun static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
66*4882a593Smuzhiyun enum pipe pipe, u32 bits)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
71*4882a593Smuzhiyun u32 interrupt_mask,
72*4882a593Smuzhiyun u32 enabled_irq_mask);
73*4882a593Smuzhiyun static inline void
ibx_enable_display_interrupt(struct drm_i915_private * dev_priv,u32 bits)74*4882a593Smuzhiyun ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun ibx_display_interrupt_update(dev_priv, bits, bits);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun static inline void
ibx_disable_display_interrupt(struct drm_i915_private * dev_priv,u32 bits)79*4882a593Smuzhiyun ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun ibx_display_interrupt_update(dev_priv, bits, 0);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
85*4882a593Smuzhiyun void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
86*4882a593Smuzhiyun void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
87*4882a593Smuzhiyun void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
88*4882a593Smuzhiyun void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
89*4882a593Smuzhiyun void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
90*4882a593Smuzhiyun void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
91*4882a593Smuzhiyun u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
94*4882a593Smuzhiyun void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
95*4882a593Smuzhiyun bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
96*4882a593Smuzhiyun void intel_synchronize_irq(struct drm_i915_private *i915);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun int intel_get_crtc_scanline(struct intel_crtc *crtc);
99*4882a593Smuzhiyun void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
100*4882a593Smuzhiyun u8 pipe_mask);
101*4882a593Smuzhiyun void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
102*4882a593Smuzhiyun u8 pipe_mask);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
105*4882a593Smuzhiyun ktime_t *vblank_time, bool in_vblank_irq);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun u32 i915_get_vblank_counter(struct drm_crtc *crtc);
108*4882a593Smuzhiyun u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun int i8xx_enable_vblank(struct drm_crtc *crtc);
111*4882a593Smuzhiyun int i915gm_enable_vblank(struct drm_crtc *crtc);
112*4882a593Smuzhiyun int i965_enable_vblank(struct drm_crtc *crtc);
113*4882a593Smuzhiyun int ilk_enable_vblank(struct drm_crtc *crtc);
114*4882a593Smuzhiyun int bdw_enable_vblank(struct drm_crtc *crtc);
115*4882a593Smuzhiyun void i8xx_disable_vblank(struct drm_crtc *crtc);
116*4882a593Smuzhiyun void i915gm_disable_vblank(struct drm_crtc *crtc);
117*4882a593Smuzhiyun void i965_disable_vblank(struct drm_crtc *crtc);
118*4882a593Smuzhiyun void ilk_disable_vblank(struct drm_crtc *crtc);
119*4882a593Smuzhiyun void bdw_disable_vblank(struct drm_crtc *crtc);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun void gen2_irq_reset(struct intel_uncore *uncore);
122*4882a593Smuzhiyun void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
123*4882a593Smuzhiyun i915_reg_t iir, i915_reg_t ier);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun void gen2_irq_init(struct intel_uncore *uncore,
126*4882a593Smuzhiyun u32 imr_val, u32 ier_val);
127*4882a593Smuzhiyun void gen3_irq_init(struct intel_uncore *uncore,
128*4882a593Smuzhiyun i915_reg_t imr, u32 imr_val,
129*4882a593Smuzhiyun i915_reg_t ier, u32 ier_val,
130*4882a593Smuzhiyun i915_reg_t iir);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
133*4882a593Smuzhiyun ({ \
134*4882a593Smuzhiyun unsigned int which_ = which; \
135*4882a593Smuzhiyun gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
136*4882a593Smuzhiyun GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
137*4882a593Smuzhiyun })
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define GEN3_IRQ_RESET(uncore, type) \
140*4882a593Smuzhiyun gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define GEN2_IRQ_RESET(uncore) \
143*4882a593Smuzhiyun gen2_irq_reset(uncore)
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
146*4882a593Smuzhiyun ({ \
147*4882a593Smuzhiyun unsigned int which_ = which; \
148*4882a593Smuzhiyun gen3_irq_init((uncore), \
149*4882a593Smuzhiyun GEN8_##type##_IMR(which_), imr_val, \
150*4882a593Smuzhiyun GEN8_##type##_IER(which_), ier_val, \
151*4882a593Smuzhiyun GEN8_##type##_IIR(which_)); \
152*4882a593Smuzhiyun })
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
155*4882a593Smuzhiyun gen3_irq_init((uncore), \
156*4882a593Smuzhiyun type##IMR, imr_val, \
157*4882a593Smuzhiyun type##IER, ier_val, \
158*4882a593Smuzhiyun type##IIR)
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
161*4882a593Smuzhiyun gen2_irq_init((uncore), imr_val, ier_val)
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun #endif /* __I915_IRQ_H__ */
164