1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Authors: 24*4882a593Smuzhiyun * Eddie Dong <eddie.dong@intel.com> 25*4882a593Smuzhiyun * Kevin Tian <kevin.tian@intel.com> 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * Contributors: 28*4882a593Smuzhiyun * Zhi Wang <zhi.a.wang@intel.com> 29*4882a593Smuzhiyun * Changbin Du <changbin.du@intel.com> 30*4882a593Smuzhiyun * Zhenyu Wang <zhenyuw@linux.intel.com> 31*4882a593Smuzhiyun * Tina Zhang <tina.zhang@intel.com> 32*4882a593Smuzhiyun * Bing Niu <bing.niu@intel.com> 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifndef __GVT_RENDER_H__ 37*4882a593Smuzhiyun #define __GVT_RENDER_H__ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct engine_mmio { 40*4882a593Smuzhiyun enum intel_engine_id id; 41*4882a593Smuzhiyun i915_reg_t reg; 42*4882a593Smuzhiyun u32 mask; 43*4882a593Smuzhiyun bool in_context; 44*4882a593Smuzhiyun u32 value; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun void intel_gvt_switch_mmio(struct intel_vgpu *pre, 48*4882a593Smuzhiyun struct intel_vgpu *next, 49*4882a593Smuzhiyun const struct intel_engine_cs *engine); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun bool is_inhibit_context(struct intel_context *ce); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 56*4882a593Smuzhiyun struct i915_request *req); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define IS_RESTORE_INHIBIT(a) \ 59*4882a593Smuzhiyun IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62