1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Authors: 24*4882a593Smuzhiyun * Ke Yu 25*4882a593Smuzhiyun * Kevin Tian <kevin.tian@intel.com> 26*4882a593Smuzhiyun * Dexuan Cui 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Contributors: 29*4882a593Smuzhiyun * Tina Zhang <tina.zhang@intel.com> 30*4882a593Smuzhiyun * Min He <min.he@intel.com> 31*4882a593Smuzhiyun * Niu Bing <bing.niu@intel.com> 32*4882a593Smuzhiyun * Zhi Wang <zhi.a.wang@intel.com> 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifndef _GVT_MMIO_H_ 37*4882a593Smuzhiyun #define _GVT_MMIO_H_ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #include <linux/types.h> 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct intel_gvt; 42*4882a593Smuzhiyun struct intel_vgpu; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define D_BDW (1 << 0) 45*4882a593Smuzhiyun #define D_SKL (1 << 1) 46*4882a593Smuzhiyun #define D_KBL (1 << 2) 47*4882a593Smuzhiyun #define D_BXT (1 << 3) 48*4882a593Smuzhiyun #define D_CFL (1 << 4) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define D_GEN9PLUS (D_SKL | D_KBL | D_BXT | D_CFL) 51*4882a593Smuzhiyun #define D_GEN8PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define D_SKL_PLUS (D_SKL | D_KBL | D_BXT | D_CFL) 54*4882a593Smuzhiyun #define D_BDW_PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define D_PRE_SKL (D_BDW) 57*4882a593Smuzhiyun #define D_ALL (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *, 60*4882a593Smuzhiyun unsigned int); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct intel_gvt_mmio_info { 63*4882a593Smuzhiyun u32 offset; 64*4882a593Smuzhiyun u64 ro_mask; 65*4882a593Smuzhiyun u32 device; 66*4882a593Smuzhiyun gvt_mmio_func read; 67*4882a593Smuzhiyun gvt_mmio_func write; 68*4882a593Smuzhiyun u32 addr_range; 69*4882a593Smuzhiyun struct hlist_node node; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun const struct intel_engine_cs * 73*4882a593Smuzhiyun intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg); 74*4882a593Smuzhiyun unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt); 75*4882a593Smuzhiyun bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun int intel_gvt_setup_mmio_info(struct intel_gvt *gvt); 78*4882a593Smuzhiyun void intel_gvt_clean_mmio_info(struct intel_gvt *gvt); 79*4882a593Smuzhiyun int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 80*4882a593Smuzhiyun int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 81*4882a593Smuzhiyun void *data); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun int intel_vgpu_init_mmio(struct intel_vgpu *vgpu); 84*4882a593Smuzhiyun void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr); 85*4882a593Smuzhiyun void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, 90*4882a593Smuzhiyun void *p_data, unsigned int bytes); 91*4882a593Smuzhiyun int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, 92*4882a593Smuzhiyun void *p_data, unsigned int bytes); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 95*4882a593Smuzhiyun void *p_data, unsigned int bytes); 96*4882a593Smuzhiyun int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 97*4882a593Smuzhiyun void *p_data, unsigned int bytes); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 100*4882a593Smuzhiyun unsigned int offset); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 103*4882a593Smuzhiyun void *pdata, unsigned int bytes, bool is_read); 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 106*4882a593Smuzhiyun void *p_data, unsigned int bytes); 107*4882a593Smuzhiyun #endif 108