1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Authors: 24*4882a593Smuzhiyun * Kevin Tian <kevin.tian@intel.com> 25*4882a593Smuzhiyun * Zhi Wang <zhi.a.wang@intel.com> 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * Contributors: 28*4882a593Smuzhiyun * Min he <min.he@intel.com> 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _GVT_INTERRUPT_H_ 33*4882a593Smuzhiyun #define _GVT_INTERRUPT_H_ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #include <linux/types.h> 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun enum intel_gvt_event_type { 38*4882a593Smuzhiyun RCS_MI_USER_INTERRUPT = 0, 39*4882a593Smuzhiyun RCS_DEBUG, 40*4882a593Smuzhiyun RCS_MMIO_SYNC_FLUSH, 41*4882a593Smuzhiyun RCS_CMD_STREAMER_ERR, 42*4882a593Smuzhiyun RCS_PIPE_CONTROL, 43*4882a593Smuzhiyun RCS_L3_PARITY_ERR, 44*4882a593Smuzhiyun RCS_WATCHDOG_EXCEEDED, 45*4882a593Smuzhiyun RCS_PAGE_DIRECTORY_FAULT, 46*4882a593Smuzhiyun RCS_AS_CONTEXT_SWITCH, 47*4882a593Smuzhiyun RCS_MONITOR_BUFF_HALF_FULL, 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun VCS_MI_USER_INTERRUPT, 50*4882a593Smuzhiyun VCS_MMIO_SYNC_FLUSH, 51*4882a593Smuzhiyun VCS_CMD_STREAMER_ERR, 52*4882a593Smuzhiyun VCS_MI_FLUSH_DW, 53*4882a593Smuzhiyun VCS_WATCHDOG_EXCEEDED, 54*4882a593Smuzhiyun VCS_PAGE_DIRECTORY_FAULT, 55*4882a593Smuzhiyun VCS_AS_CONTEXT_SWITCH, 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun VCS2_MI_USER_INTERRUPT, 58*4882a593Smuzhiyun VCS2_MI_FLUSH_DW, 59*4882a593Smuzhiyun VCS2_AS_CONTEXT_SWITCH, 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun BCS_MI_USER_INTERRUPT, 62*4882a593Smuzhiyun BCS_MMIO_SYNC_FLUSH, 63*4882a593Smuzhiyun BCS_CMD_STREAMER_ERR, 64*4882a593Smuzhiyun BCS_MI_FLUSH_DW, 65*4882a593Smuzhiyun BCS_PAGE_DIRECTORY_FAULT, 66*4882a593Smuzhiyun BCS_AS_CONTEXT_SWITCH, 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun VECS_MI_USER_INTERRUPT, 69*4882a593Smuzhiyun VECS_MI_FLUSH_DW, 70*4882a593Smuzhiyun VECS_AS_CONTEXT_SWITCH, 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun PIPE_A_FIFO_UNDERRUN, 73*4882a593Smuzhiyun PIPE_B_FIFO_UNDERRUN, 74*4882a593Smuzhiyun PIPE_A_CRC_ERR, 75*4882a593Smuzhiyun PIPE_B_CRC_ERR, 76*4882a593Smuzhiyun PIPE_A_CRC_DONE, 77*4882a593Smuzhiyun PIPE_B_CRC_DONE, 78*4882a593Smuzhiyun PIPE_A_ODD_FIELD, 79*4882a593Smuzhiyun PIPE_B_ODD_FIELD, 80*4882a593Smuzhiyun PIPE_A_EVEN_FIELD, 81*4882a593Smuzhiyun PIPE_B_EVEN_FIELD, 82*4882a593Smuzhiyun PIPE_A_LINE_COMPARE, 83*4882a593Smuzhiyun PIPE_B_LINE_COMPARE, 84*4882a593Smuzhiyun PIPE_C_LINE_COMPARE, 85*4882a593Smuzhiyun PIPE_A_VBLANK, 86*4882a593Smuzhiyun PIPE_B_VBLANK, 87*4882a593Smuzhiyun PIPE_C_VBLANK, 88*4882a593Smuzhiyun PIPE_A_VSYNC, 89*4882a593Smuzhiyun PIPE_B_VSYNC, 90*4882a593Smuzhiyun PIPE_C_VSYNC, 91*4882a593Smuzhiyun PRIMARY_A_FLIP_DONE, 92*4882a593Smuzhiyun PRIMARY_B_FLIP_DONE, 93*4882a593Smuzhiyun PRIMARY_C_FLIP_DONE, 94*4882a593Smuzhiyun SPRITE_A_FLIP_DONE, 95*4882a593Smuzhiyun SPRITE_B_FLIP_DONE, 96*4882a593Smuzhiyun SPRITE_C_FLIP_DONE, 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun PCU_THERMAL, 99*4882a593Smuzhiyun PCU_PCODE2DRIVER_MAILBOX, 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun DPST_PHASE_IN, 102*4882a593Smuzhiyun DPST_HISTOGRAM, 103*4882a593Smuzhiyun GSE, 104*4882a593Smuzhiyun DP_A_HOTPLUG, 105*4882a593Smuzhiyun AUX_CHANNEL_A, 106*4882a593Smuzhiyun PERF_COUNTER, 107*4882a593Smuzhiyun POISON, 108*4882a593Smuzhiyun GTT_FAULT, 109*4882a593Smuzhiyun ERROR_INTERRUPT_COMBINED, 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun FDI_RX_INTERRUPTS_TRANSCODER_A, 112*4882a593Smuzhiyun AUDIO_CP_CHANGE_TRANSCODER_A, 113*4882a593Smuzhiyun AUDIO_CP_REQUEST_TRANSCODER_A, 114*4882a593Smuzhiyun FDI_RX_INTERRUPTS_TRANSCODER_B, 115*4882a593Smuzhiyun AUDIO_CP_CHANGE_TRANSCODER_B, 116*4882a593Smuzhiyun AUDIO_CP_REQUEST_TRANSCODER_B, 117*4882a593Smuzhiyun FDI_RX_INTERRUPTS_TRANSCODER_C, 118*4882a593Smuzhiyun AUDIO_CP_CHANGE_TRANSCODER_C, 119*4882a593Smuzhiyun AUDIO_CP_REQUEST_TRANSCODER_C, 120*4882a593Smuzhiyun ERR_AND_DBG, 121*4882a593Smuzhiyun GMBUS, 122*4882a593Smuzhiyun SDVO_B_HOTPLUG, 123*4882a593Smuzhiyun CRT_HOTPLUG, 124*4882a593Smuzhiyun DP_B_HOTPLUG, 125*4882a593Smuzhiyun DP_C_HOTPLUG, 126*4882a593Smuzhiyun DP_D_HOTPLUG, 127*4882a593Smuzhiyun AUX_CHANNEL_B, 128*4882a593Smuzhiyun AUX_CHANNEL_C, 129*4882a593Smuzhiyun AUX_CHANNEL_D, 130*4882a593Smuzhiyun AUDIO_POWER_STATE_CHANGE_B, 131*4882a593Smuzhiyun AUDIO_POWER_STATE_CHANGE_C, 132*4882a593Smuzhiyun AUDIO_POWER_STATE_CHANGE_D, 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun INTEL_GVT_EVENT_RESERVED, 135*4882a593Smuzhiyun INTEL_GVT_EVENT_MAX, 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun struct intel_gvt_irq; 139*4882a593Smuzhiyun struct intel_gvt; 140*4882a593Smuzhiyun struct intel_vgpu; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq, 143*4882a593Smuzhiyun enum intel_gvt_event_type event, struct intel_vgpu *vgpu); 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct intel_gvt_irq_ops { 146*4882a593Smuzhiyun void (*init_irq)(struct intel_gvt_irq *irq); 147*4882a593Smuzhiyun void (*check_pending_irq)(struct intel_vgpu *vgpu); 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* the list of physical interrupt control register groups */ 151*4882a593Smuzhiyun enum intel_gvt_irq_type { 152*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_GT, 153*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DPY, 154*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_PCH, 155*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_PM, 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_MASTER, 158*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_GT0, 159*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_GT1, 160*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_GT2, 161*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_GT3, 162*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DE_PIPE_A, 163*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DE_PIPE_B, 164*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DE_PIPE_C, 165*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DE_PORT, 166*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_DE_MISC, 167*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_AUD, 168*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_PCU, 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun INTEL_GVT_IRQ_INFO_MAX, 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define INTEL_GVT_IRQ_BITWIDTH 32 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* device specific interrupt bit definitions */ 176*4882a593Smuzhiyun struct intel_gvt_irq_info { 177*4882a593Smuzhiyun char *name; 178*4882a593Smuzhiyun i915_reg_t reg_base; 179*4882a593Smuzhiyun enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 180*4882a593Smuzhiyun unsigned long warned; 181*4882a593Smuzhiyun int group; 182*4882a593Smuzhiyun DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 183*4882a593Smuzhiyun bool has_upstream_irq; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* per-event information */ 187*4882a593Smuzhiyun struct intel_gvt_event_info { 188*4882a593Smuzhiyun int bit; /* map to register bit */ 189*4882a593Smuzhiyun int policy; /* forwarding policy */ 190*4882a593Smuzhiyun struct intel_gvt_irq_info *info; /* register info */ 191*4882a593Smuzhiyun gvt_event_virt_handler_t v_handler; /* for v_event */ 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun struct intel_gvt_irq_map { 195*4882a593Smuzhiyun int up_irq_group; 196*4882a593Smuzhiyun int up_irq_bit; 197*4882a593Smuzhiyun int down_irq_group; 198*4882a593Smuzhiyun u32 down_irq_bitmask; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun struct intel_gvt_vblank_timer { 202*4882a593Smuzhiyun struct hrtimer timer; 203*4882a593Smuzhiyun u64 period; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* structure containing device specific IRQ state */ 207*4882a593Smuzhiyun struct intel_gvt_irq { 208*4882a593Smuzhiyun struct intel_gvt_irq_ops *ops; 209*4882a593Smuzhiyun struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX]; 210*4882a593Smuzhiyun DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX); 211*4882a593Smuzhiyun struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX]; 212*4882a593Smuzhiyun DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX); 213*4882a593Smuzhiyun struct intel_gvt_irq_map *irq_map; 214*4882a593Smuzhiyun struct intel_gvt_vblank_timer vblank_timer; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun int intel_gvt_init_irq(struct intel_gvt *gvt); 218*4882a593Smuzhiyun void intel_gvt_clean_irq(struct intel_gvt *gvt); 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 221*4882a593Smuzhiyun enum intel_gvt_event_type event); 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 224*4882a593Smuzhiyun void *p_data, unsigned int bytes); 225*4882a593Smuzhiyun int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 226*4882a593Smuzhiyun unsigned int reg, void *p_data, unsigned int bytes); 227*4882a593Smuzhiyun int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 228*4882a593Smuzhiyun unsigned int reg, void *p_data, unsigned int bytes); 229*4882a593Smuzhiyun int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 230*4882a593Smuzhiyun unsigned int reg, void *p_data, unsigned int bytes); 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun int gvt_ring_id_to_pipe_control_notify_event(int ring_id); 233*4882a593Smuzhiyun int gvt_ring_id_to_mi_flush_dw_event(int ring_id); 234*4882a593Smuzhiyun int gvt_ring_id_to_mi_user_interrupt_event(int ring_id); 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #endif /* _GVT_INTERRUPT_H_ */ 237