1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Authors: 24*4882a593Smuzhiyun * Ke Yu 25*4882a593Smuzhiyun * Zhiyuan Lv <zhiyuan.lv@intel.com> 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * Contributors: 28*4882a593Smuzhiyun * Terrence Xu <terrence.xu@intel.com> 29*4882a593Smuzhiyun * Changbin Du <changbin.du@intel.com> 30*4882a593Smuzhiyun * Bing Niu <bing.niu@intel.com> 31*4882a593Smuzhiyun * Zhi Wang <zhi.a.wang@intel.com> 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef _GVT_EDID_H_ 36*4882a593Smuzhiyun #define _GVT_EDID_H_ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include <linux/types.h> 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct intel_vgpu; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define EDID_SIZE 128 43*4882a593Smuzhiyun #define EDID_ADDR 0x50 /* Linux hvm EDID addr */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define GVT_AUX_NATIVE_WRITE 0x8 46*4882a593Smuzhiyun #define GVT_AUX_NATIVE_READ 0x9 47*4882a593Smuzhiyun #define GVT_AUX_I2C_WRITE 0x0 48*4882a593Smuzhiyun #define GVT_AUX_I2C_READ 0x1 49*4882a593Smuzhiyun #define GVT_AUX_I2C_STATUS 0x2 50*4882a593Smuzhiyun #define GVT_AUX_I2C_MOT 0x4 51*4882a593Smuzhiyun #define GVT_AUX_I2C_REPLY_ACK 0x0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct intel_vgpu_edid_data { 54*4882a593Smuzhiyun bool data_valid; 55*4882a593Smuzhiyun unsigned char edid_block[EDID_SIZE]; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum gmbus_cycle_type { 59*4882a593Smuzhiyun GMBUS_NOCYCLE = 0x0, 60*4882a593Smuzhiyun NIDX_NS_W = 0x1, 61*4882a593Smuzhiyun IDX_NS_W = 0x3, 62*4882a593Smuzhiyun GMBUS_STOP = 0x4, 63*4882a593Smuzhiyun NIDX_STOP = 0x5, 64*4882a593Smuzhiyun IDX_STOP = 0x7 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * States of GMBUS 69*4882a593Smuzhiyun * 70*4882a593Smuzhiyun * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS 71*4882a593Smuzhiyun * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are 72*4882a593Smuzhiyun * not considered here. Below describes the usage of GMBUS registers that are 73*4882a593Smuzhiyun * cared by the EDID virtualization 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * GMBUS0: 76*4882a593Smuzhiyun * R/W 77*4882a593Smuzhiyun * port selection. value of bit0 - bit2 corresponds to the GPIO registers. 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * GMBUS1: 80*4882a593Smuzhiyun * R/W Protect 81*4882a593Smuzhiyun * Command and Status. 82*4882a593Smuzhiyun * bit0 is the direction bit: 1 is read; 0 is write. 83*4882a593Smuzhiyun * bit1 - bit7 is slave 7-bit address. 84*4882a593Smuzhiyun * bit16 - bit24 total byte count (ignore?) 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * GMBUS2: 87*4882a593Smuzhiyun * Most of bits are read only except bit 15 (IN_USE) 88*4882a593Smuzhiyun * Status register 89*4882a593Smuzhiyun * bit0 - bit8 current byte count 90*4882a593Smuzhiyun * bit 11: hardware ready; 91*4882a593Smuzhiyun * 92*4882a593Smuzhiyun * GMBUS3: 93*4882a593Smuzhiyun * Read/Write 94*4882a593Smuzhiyun * Data for transfer 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* From hw specs, Other phases like START, ADDRESS, INDEX 98*4882a593Smuzhiyun * are invisible to GMBUS MMIO interface. So no definitions 99*4882a593Smuzhiyun * in below enum types 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun enum gvt_gmbus_phase { 102*4882a593Smuzhiyun GMBUS_IDLE_PHASE = 0, 103*4882a593Smuzhiyun GMBUS_DATA_PHASE, 104*4882a593Smuzhiyun GMBUS_WAIT_PHASE, 105*4882a593Smuzhiyun //GMBUS_STOP_PHASE, 106*4882a593Smuzhiyun GMBUS_MAX_PHASE 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct intel_vgpu_i2c_gmbus { 110*4882a593Smuzhiyun unsigned int total_byte_count; /* from GMBUS1 */ 111*4882a593Smuzhiyun enum gmbus_cycle_type cycle_type; 112*4882a593Smuzhiyun enum gvt_gmbus_phase phase; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct intel_vgpu_i2c_aux_ch { 116*4882a593Smuzhiyun bool i2c_over_aux_ch; 117*4882a593Smuzhiyun bool aux_ch_mot; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun enum i2c_state { 121*4882a593Smuzhiyun I2C_NOT_SPECIFIED = 0, 122*4882a593Smuzhiyun I2C_GMBUS = 1, 123*4882a593Smuzhiyun I2C_AUX_CH = 2 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* I2C sequences cannot interleave. 127*4882a593Smuzhiyun * GMBUS and AUX_CH sequences cannot interleave. 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun struct intel_vgpu_i2c_edid { 130*4882a593Smuzhiyun enum i2c_state state; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun unsigned int port; 133*4882a593Smuzhiyun bool slave_selected; 134*4882a593Smuzhiyun bool edid_available; 135*4882a593Smuzhiyun unsigned int current_edid_read; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun struct intel_vgpu_i2c_gmbus gmbus; 138*4882a593Smuzhiyun struct intel_vgpu_i2c_aux_ch aux_ch; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu); 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, 144*4882a593Smuzhiyun unsigned int offset, void *p_data, unsigned int bytes); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, 147*4882a593Smuzhiyun unsigned int offset, void *p_data, unsigned int bytes); 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, 150*4882a593Smuzhiyun int port_idx, 151*4882a593Smuzhiyun unsigned int offset, 152*4882a593Smuzhiyun void *p_data); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #endif /*_GVT_EDID_H_*/ 155