xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/intel_reset.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * SPDX-License-Identifier: MIT
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright © 2008-2018 Intel Corporation
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef I915_RESET_H
8*4882a593Smuzhiyun #define I915_RESET_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/compiler.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/srcu.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include "intel_engine_types.h"
15*4882a593Smuzhiyun #include "intel_reset_types.h"
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct i915_request;
18*4882a593Smuzhiyun struct intel_engine_cs;
19*4882a593Smuzhiyun struct intel_gt;
20*4882a593Smuzhiyun struct intel_guc;
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun void intel_gt_init_reset(struct intel_gt *gt);
23*4882a593Smuzhiyun void intel_gt_fini_reset(struct intel_gt *gt);
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun __printf(4, 5)
26*4882a593Smuzhiyun void intel_gt_handle_error(struct intel_gt *gt,
27*4882a593Smuzhiyun 			   intel_engine_mask_t engine_mask,
28*4882a593Smuzhiyun 			   unsigned long flags,
29*4882a593Smuzhiyun 			   const char *fmt, ...);
30*4882a593Smuzhiyun #define I915_ERROR_CAPTURE BIT(0)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun void intel_gt_reset(struct intel_gt *gt,
33*4882a593Smuzhiyun 		    intel_engine_mask_t stalled_mask,
34*4882a593Smuzhiyun 		    const char *reason);
35*4882a593Smuzhiyun int intel_engine_reset(struct intel_engine_cs *engine,
36*4882a593Smuzhiyun 		       const char *reason);
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun void __i915_request_reset(struct i915_request *rq, bool guilty);
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun int __must_check intel_gt_reset_trylock(struct intel_gt *gt, int *srcu);
41*4882a593Smuzhiyun void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun void intel_gt_set_wedged(struct intel_gt *gt);
44*4882a593Smuzhiyun bool intel_gt_unset_wedged(struct intel_gt *gt);
45*4882a593Smuzhiyun int intel_gt_terminally_wedged(struct intel_gt *gt);
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun  * There's no unset_wedged_on_init paired with this one.
49*4882a593Smuzhiyun  * Once we're wedged on init, there's no going back.
50*4882a593Smuzhiyun  * Same thing for unset_wedged_on_fini.
51*4882a593Smuzhiyun  */
52*4882a593Smuzhiyun void intel_gt_set_wedged_on_init(struct intel_gt *gt);
53*4882a593Smuzhiyun void intel_gt_set_wedged_on_fini(struct intel_gt *gt);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun int intel_reset_guc(struct intel_gt *gt);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct intel_wedge_me {
60*4882a593Smuzhiyun 	struct delayed_work work;
61*4882a593Smuzhiyun 	struct intel_gt *gt;
62*4882a593Smuzhiyun 	const char *name;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun void __intel_init_wedge(struct intel_wedge_me *w,
66*4882a593Smuzhiyun 			struct intel_gt *gt,
67*4882a593Smuzhiyun 			long timeout,
68*4882a593Smuzhiyun 			const char *name);
69*4882a593Smuzhiyun void __intel_fini_wedge(struct intel_wedge_me *w);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define intel_wedge_on_timeout(W, GT, TIMEOUT)				\
72*4882a593Smuzhiyun 	for (__intel_init_wedge((W), (GT), (TIMEOUT), __func__);	\
73*4882a593Smuzhiyun 	     (W)->gt;							\
74*4882a593Smuzhiyun 	     __intel_fini_wedge((W)))
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun bool intel_has_gpu_reset(const struct intel_gt *gt);
77*4882a593Smuzhiyun bool intel_has_reset_engine(const struct intel_gt *gt);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #endif /* I915_RESET_H */
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