1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright © 2014 Intel Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef _INTEL_RENDERSTATE_H_ 25*4882a593Smuzhiyun #define _INTEL_RENDERSTATE_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <linux/types.h> 28*4882a593Smuzhiyun #include "i915_gem.h" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct i915_request; 31*4882a593Smuzhiyun struct intel_context; 32*4882a593Smuzhiyun struct i915_vma; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct intel_renderstate_rodata { 35*4882a593Smuzhiyun const u32 *reloc; 36*4882a593Smuzhiyun const u32 *batch; 37*4882a593Smuzhiyun const u32 batch_items; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define RO_RENDERSTATE(_g) \ 41*4882a593Smuzhiyun const struct intel_renderstate_rodata gen ## _g ## _null_state = { \ 42*4882a593Smuzhiyun .reloc = gen ## _g ## _null_state_relocs, \ 43*4882a593Smuzhiyun .batch = gen ## _g ## _null_state_batch, \ 44*4882a593Smuzhiyun .batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \ 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun extern const struct intel_renderstate_rodata gen6_null_state; 48*4882a593Smuzhiyun extern const struct intel_renderstate_rodata gen7_null_state; 49*4882a593Smuzhiyun extern const struct intel_renderstate_rodata gen8_null_state; 50*4882a593Smuzhiyun extern const struct intel_renderstate_rodata gen9_null_state; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct intel_renderstate { 53*4882a593Smuzhiyun struct i915_gem_ww_ctx ww; 54*4882a593Smuzhiyun const struct intel_renderstate_rodata *rodata; 55*4882a593Smuzhiyun struct i915_vma *vma; 56*4882a593Smuzhiyun u32 batch_offset; 57*4882a593Smuzhiyun u32 batch_size; 58*4882a593Smuzhiyun u32 aux_offset; 59*4882a593Smuzhiyun u32 aux_size; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun int intel_renderstate_init(struct intel_renderstate *so, 63*4882a593Smuzhiyun struct intel_context *ce); 64*4882a593Smuzhiyun int intel_renderstate_emit(struct intel_renderstate *so, 65*4882a593Smuzhiyun struct i915_request *rq); 66*4882a593Smuzhiyun void intel_renderstate_fini(struct intel_renderstate *so, 67*4882a593Smuzhiyun struct intel_context *ce); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* _INTEL_RENDERSTATE_H_ */ 70