1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright © 2014 Intel Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 13*4882a593Smuzhiyun * Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef _INTEL_LRC_H_ 25*4882a593Smuzhiyun #define _INTEL_LRC_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <linux/types.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct drm_printer; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct drm_i915_private; 32*4882a593Smuzhiyun struct i915_gem_context; 33*4882a593Smuzhiyun struct i915_request; 34*4882a593Smuzhiyun struct intel_context; 35*4882a593Smuzhiyun struct intel_engine_cs; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Execlists regs */ 38*4882a593Smuzhiyun #define RING_ELSP(base) _MMIO((base) + 0x230) 39*4882a593Smuzhiyun #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 40*4882a593Smuzhiyun #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 41*4882a593Smuzhiyun #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 42*4882a593Smuzhiyun #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) 43*4882a593Smuzhiyun #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) 44*4882a593Smuzhiyun #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) 45*4882a593Smuzhiyun #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2) 46*4882a593Smuzhiyun #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8) 47*4882a593Smuzhiyun #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 48*4882a593Smuzhiyun #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 49*4882a593Smuzhiyun #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define EL_CTRL_LOAD (1 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* The docs specify that the write pointer wraps around after 5h, "After status 54*4882a593Smuzhiyun * is written out to the last available status QW at offset 5h, this pointer 55*4882a593Smuzhiyun * wraps to 0." 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * Therefore, one must infer than even though there are 3 bits available, 6 and 58*4882a593Smuzhiyun * 7 appear to be * reserved. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define GEN8_CSB_ENTRIES 6 61*4882a593Smuzhiyun #define GEN8_CSB_PTR_MASK 0x7 62*4882a593Smuzhiyun #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 63*4882a593Smuzhiyun #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define GEN11_CSB_ENTRIES 12 66*4882a593Smuzhiyun #define GEN11_CSB_PTR_MASK 0xf 67*4882a593Smuzhiyun #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) 68*4882a593Smuzhiyun #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 71*4882a593Smuzhiyun #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 72*4882a593Smuzhiyun #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 73*4882a593Smuzhiyun /* in Gen12 ID 0x7FF is reserved to indicate idle */ 74*4882a593Smuzhiyun #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun enum { 77*4882a593Smuzhiyun INTEL_CONTEXT_SCHEDULE_IN = 0, 78*4882a593Smuzhiyun INTEL_CONTEXT_SCHEDULE_OUT, 79*4882a593Smuzhiyun INTEL_CONTEXT_SCHEDULE_PREEMPTED, 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Logical Rings */ 83*4882a593Smuzhiyun void intel_logical_ring_cleanup(struct intel_engine_cs *engine); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun int intel_execlists_submission_setup(struct intel_engine_cs *engine); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Logical Ring Contexts */ 88*4882a593Smuzhiyun /* At the start of the context image is its per-process HWS page */ 89*4882a593Smuzhiyun #define LRC_PPHWSP_PN (0) 90*4882a593Smuzhiyun #define LRC_PPHWSP_SZ (1) 91*4882a593Smuzhiyun /* After the PPHWSP we have the logical state for the context */ 92*4882a593Smuzhiyun #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 93*4882a593Smuzhiyun #define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Space within PPHWSP reserved to be used as scratch */ 96*4882a593Smuzhiyun #define LRC_PPHWSP_SCRATCH 0x34 97*4882a593Smuzhiyun #define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32)) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun void intel_execlists_set_default_submission(struct intel_engine_cs *engine); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun void intel_lr_context_reset(struct intel_engine_cs *engine, 102*4882a593Smuzhiyun struct intel_context *ce, 103*4882a593Smuzhiyun u32 head, 104*4882a593Smuzhiyun bool scrub); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun void intel_execlists_show_requests(struct intel_engine_cs *engine, 107*4882a593Smuzhiyun struct drm_printer *m, 108*4882a593Smuzhiyun void (*show_request)(struct drm_printer *m, 109*4882a593Smuzhiyun struct i915_request *rq, 110*4882a593Smuzhiyun const char *prefix), 111*4882a593Smuzhiyun unsigned int max); 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun struct intel_context * 114*4882a593Smuzhiyun intel_execlists_create_virtual(struct intel_engine_cs **siblings, 115*4882a593Smuzhiyun unsigned int count); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun struct intel_context * 118*4882a593Smuzhiyun intel_execlists_clone_virtual(struct intel_engine_cs *src); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, 121*4882a593Smuzhiyun const struct intel_engine_cs *master, 122*4882a593Smuzhiyun const struct intel_engine_cs *sibling); 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun struct intel_engine_cs * 125*4882a593Smuzhiyun intel_virtual_engine_get_sibling(struct intel_engine_cs *engine, 126*4882a593Smuzhiyun unsigned int sibling); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun bool 129*4882a593Smuzhiyun intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine); 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* _INTEL_LRC_H_ */ 132