1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright © 2016 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun * Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
27*4882a593Smuzhiyun #include <drm/drm_dp_dual_mode_helper.h>
28*4882a593Smuzhiyun #include <drm/drm_edid.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "intel_display_types.h"
31*4882a593Smuzhiyun #include "intel_dp.h"
32*4882a593Smuzhiyun #include "intel_lspcon.h"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* LSPCON OUI Vendor ID(signatures) */
35*4882a593Smuzhiyun #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
36*4882a593Smuzhiyun #define LSPCON_VENDOR_MCA_OUI 0x0060AD
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* AUX addresses to write MCA AVI IF */
39*4882a593Smuzhiyun #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
40*4882a593Smuzhiyun #define LSPCON_MCA_AVI_IF_CTRL 0x5DF
41*4882a593Smuzhiyun #define LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
42*4882a593Smuzhiyun #define LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* AUX addresses to write Parade AVI IF */
45*4882a593Smuzhiyun #define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516
46*4882a593Smuzhiyun #define LSPCON_PARADE_AVI_IF_CTRL 0x51E
47*4882a593Smuzhiyun #define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7)
48*4882a593Smuzhiyun #define LSPCON_PARADE_AVI_IF_DATA_SIZE 32
49*4882a593Smuzhiyun
lspcon_to_intel_dp(struct intel_lspcon * lspcon)50*4882a593Smuzhiyun static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct intel_digital_port *dig_port =
53*4882a593Smuzhiyun container_of(lspcon, struct intel_digital_port, lspcon);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return &dig_port->dp;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
lspcon_mode_name(enum drm_lspcon_mode mode)58*4882a593Smuzhiyun static const char *lspcon_mode_name(enum drm_lspcon_mode mode)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun switch (mode) {
61*4882a593Smuzhiyun case DRM_LSPCON_MODE_PCON:
62*4882a593Smuzhiyun return "PCON";
63*4882a593Smuzhiyun case DRM_LSPCON_MODE_LS:
64*4882a593Smuzhiyun return "LS";
65*4882a593Smuzhiyun case DRM_LSPCON_MODE_INVALID:
66*4882a593Smuzhiyun return "INVALID";
67*4882a593Smuzhiyun default:
68*4882a593Smuzhiyun MISSING_CASE(mode);
69*4882a593Smuzhiyun return "INVALID";
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
lspcon_detect_vendor(struct intel_lspcon * lspcon)73*4882a593Smuzhiyun static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
76*4882a593Smuzhiyun struct drm_dp_dpcd_ident *ident;
77*4882a593Smuzhiyun u32 vendor_oui;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) {
80*4882a593Smuzhiyun DRM_ERROR("Can't read description\n");
81*4882a593Smuzhiyun return false;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ident = &dp->desc.ident;
85*4882a593Smuzhiyun vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) |
86*4882a593Smuzhiyun ident->oui[2];
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun switch (vendor_oui) {
89*4882a593Smuzhiyun case LSPCON_VENDOR_MCA_OUI:
90*4882a593Smuzhiyun lspcon->vendor = LSPCON_VENDOR_MCA;
91*4882a593Smuzhiyun DRM_DEBUG_KMS("Vendor: Mega Chips\n");
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun case LSPCON_VENDOR_PARADE_OUI:
95*4882a593Smuzhiyun lspcon->vendor = LSPCON_VENDOR_PARADE;
96*4882a593Smuzhiyun DRM_DEBUG_KMS("Vendor: Parade Tech\n");
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun default:
100*4882a593Smuzhiyun DRM_ERROR("Invalid/Unknown vendor OUI\n");
101*4882a593Smuzhiyun return false;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return true;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
lspcon_get_current_mode(struct intel_lspcon * lspcon)107*4882a593Smuzhiyun static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun enum drm_lspcon_mode current_mode;
110*4882a593Smuzhiyun struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (drm_lspcon_get_mode(adapter, ¤t_mode)) {
113*4882a593Smuzhiyun DRM_DEBUG_KMS("Error reading LSPCON mode\n");
114*4882a593Smuzhiyun return DRM_LSPCON_MODE_INVALID;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun return current_mode;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
lspcon_wait_mode(struct intel_lspcon * lspcon,enum drm_lspcon_mode mode)119*4882a593Smuzhiyun static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
120*4882a593Smuzhiyun enum drm_lspcon_mode mode)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun enum drm_lspcon_mode current_mode;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun current_mode = lspcon_get_current_mode(lspcon);
125*4882a593Smuzhiyun if (current_mode == mode)
126*4882a593Smuzhiyun goto out;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
129*4882a593Smuzhiyun lspcon_mode_name(mode));
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400);
132*4882a593Smuzhiyun if (current_mode != mode)
133*4882a593Smuzhiyun DRM_ERROR("LSPCON mode hasn't settled\n");
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun out:
136*4882a593Smuzhiyun DRM_DEBUG_KMS("Current LSPCON mode %s\n",
137*4882a593Smuzhiyun lspcon_mode_name(current_mode));
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun return current_mode;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
lspcon_change_mode(struct intel_lspcon * lspcon,enum drm_lspcon_mode mode)142*4882a593Smuzhiyun static int lspcon_change_mode(struct intel_lspcon *lspcon,
143*4882a593Smuzhiyun enum drm_lspcon_mode mode)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun int err;
146*4882a593Smuzhiyun enum drm_lspcon_mode current_mode;
147*4882a593Smuzhiyun struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun err = drm_lspcon_get_mode(adapter, ¤t_mode);
150*4882a593Smuzhiyun if (err) {
151*4882a593Smuzhiyun DRM_ERROR("Error reading LSPCON mode\n");
152*4882a593Smuzhiyun return err;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (current_mode == mode) {
156*4882a593Smuzhiyun DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n");
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun err = drm_lspcon_set_mode(adapter, mode);
161*4882a593Smuzhiyun if (err < 0) {
162*4882a593Smuzhiyun DRM_ERROR("LSPCON mode change failed\n");
163*4882a593Smuzhiyun return err;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun lspcon->mode = mode;
167*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON mode changed done\n");
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
lspcon_wake_native_aux_ch(struct intel_lspcon * lspcon)171*4882a593Smuzhiyun static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun u8 rev;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
176*4882a593Smuzhiyun &rev) != 1) {
177*4882a593Smuzhiyun DRM_DEBUG_KMS("Native AUX CH down\n");
178*4882a593Smuzhiyun return false;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n",
182*4882a593Smuzhiyun rev >> 4, rev & 0xf);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return true;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
lspcon_ycbcr420_config(struct drm_connector * connector,struct intel_crtc_state * crtc_state)187*4882a593Smuzhiyun void lspcon_ycbcr420_config(struct drm_connector *connector,
188*4882a593Smuzhiyun struct intel_crtc_state *crtc_state)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun const struct drm_display_info *info = &connector->display_info;
191*4882a593Smuzhiyun const struct drm_display_mode *adjusted_mode =
192*4882a593Smuzhiyun &crtc_state->hw.adjusted_mode;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (drm_mode_is_420_only(info, adjusted_mode) &&
195*4882a593Smuzhiyun connector->ycbcr_420_allowed) {
196*4882a593Smuzhiyun crtc_state->port_clock /= 2;
197*4882a593Smuzhiyun crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
198*4882a593Smuzhiyun crtc_state->lspcon_downsampling = true;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
lspcon_probe(struct intel_lspcon * lspcon)202*4882a593Smuzhiyun static bool lspcon_probe(struct intel_lspcon *lspcon)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun int retry;
205*4882a593Smuzhiyun enum drm_dp_dual_mode_type adaptor_type;
206*4882a593Smuzhiyun struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc;
207*4882a593Smuzhiyun enum drm_lspcon_mode expected_mode;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun expected_mode = lspcon_wake_native_aux_ch(lspcon) ?
210*4882a593Smuzhiyun DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Lets probe the adaptor and check its type */
213*4882a593Smuzhiyun for (retry = 0; retry < 6; retry++) {
214*4882a593Smuzhiyun if (retry)
215*4882a593Smuzhiyun usleep_range(500, 1000);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun adaptor_type = drm_dp_dual_mode_detect(adapter);
218*4882a593Smuzhiyun if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON)
219*4882a593Smuzhiyun break;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
223*4882a593Smuzhiyun DRM_DEBUG_KMS("No LSPCON detected, found %s\n",
224*4882a593Smuzhiyun drm_dp_get_dual_mode_type_name(adaptor_type));
225*4882a593Smuzhiyun return false;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* Yay ... got a LSPCON device */
229*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON detected\n");
230*4882a593Smuzhiyun lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /*
233*4882a593Smuzhiyun * In the SW state machine, lets Put LSPCON in PCON mode only.
234*4882a593Smuzhiyun * In this way, it will work with both HDMI 1.4 sinks as well as HDMI
235*4882a593Smuzhiyun * 2.0 sinks.
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun if (lspcon->mode != DRM_LSPCON_MODE_PCON) {
238*4882a593Smuzhiyun if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
239*4882a593Smuzhiyun DRM_ERROR("LSPCON mode change to PCON failed\n");
240*4882a593Smuzhiyun return false;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun return true;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
lspcon_resume_in_pcon_wa(struct intel_lspcon * lspcon)246*4882a593Smuzhiyun static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
249*4882a593Smuzhiyun struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
250*4882a593Smuzhiyun unsigned long start = jiffies;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun while (1) {
253*4882a593Smuzhiyun if (intel_digital_port_connected(&dig_port->base)) {
254*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
255*4882a593Smuzhiyun jiffies_to_msecs(jiffies - start));
256*4882a593Smuzhiyun return;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (time_after(jiffies, start + msecs_to_jiffies(1000)))
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun usleep_range(10000, 15000);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
lspcon_parade_fw_ready(struct drm_dp_aux * aux)268*4882a593Smuzhiyun static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun u8 avi_if_ctrl;
271*4882a593Smuzhiyun u8 retry;
272*4882a593Smuzhiyun ssize_t ret;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /* Check if LSPCON FW is ready for data */
275*4882a593Smuzhiyun for (retry = 0; retry < 5; retry++) {
276*4882a593Smuzhiyun if (retry)
277*4882a593Smuzhiyun usleep_range(200, 300);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
280*4882a593Smuzhiyun &avi_if_ctrl, 1);
281*4882a593Smuzhiyun if (ret < 0) {
282*4882a593Smuzhiyun DRM_ERROR("Failed to read AVI IF control\n");
283*4882a593Smuzhiyun return false;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0)
287*4882a593Smuzhiyun return true;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun DRM_ERROR("Parade FW not ready to accept AVI IF\n");
291*4882a593Smuzhiyun return false;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
_lspcon_parade_write_infoframe_blocks(struct drm_dp_aux * aux,u8 * avi_buf)294*4882a593Smuzhiyun static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
295*4882a593Smuzhiyun u8 *avi_buf)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun u8 avi_if_ctrl;
298*4882a593Smuzhiyun u8 block_count = 0;
299*4882a593Smuzhiyun u8 *data;
300*4882a593Smuzhiyun u16 reg;
301*4882a593Smuzhiyun ssize_t ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun while (block_count < 4) {
304*4882a593Smuzhiyun if (!lspcon_parade_fw_ready(aux)) {
305*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
306*4882a593Smuzhiyun block_count);
307*4882a593Smuzhiyun return false;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
311*4882a593Smuzhiyun data = avi_buf + block_count * 8;
312*4882a593Smuzhiyun ret = drm_dp_dpcd_write(aux, reg, data, 8);
313*4882a593Smuzhiyun if (ret < 0) {
314*4882a593Smuzhiyun DRM_ERROR("Failed to write AVI IF block %d\n",
315*4882a593Smuzhiyun block_count);
316*4882a593Smuzhiyun return false;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun /*
320*4882a593Smuzhiyun * Once a block of data is written, we have to inform the FW
321*4882a593Smuzhiyun * about this by writing into avi infoframe control register:
322*4882a593Smuzhiyun * - set the kickoff bit[7] to 1
323*4882a593Smuzhiyun * - write the block no. to bits[1:0]
324*4882a593Smuzhiyun */
325*4882a593Smuzhiyun reg = LSPCON_PARADE_AVI_IF_CTRL;
326*4882a593Smuzhiyun avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
327*4882a593Smuzhiyun ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
328*4882a593Smuzhiyun if (ret < 0) {
329*4882a593Smuzhiyun DRM_ERROR("Failed to update (0x%x), block %d\n",
330*4882a593Smuzhiyun reg, block_count);
331*4882a593Smuzhiyun return false;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun block_count++;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
338*4882a593Smuzhiyun return true;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
_lspcon_write_avi_infoframe_parade(struct drm_dp_aux * aux,const u8 * frame,ssize_t len)341*4882a593Smuzhiyun static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
342*4882a593Smuzhiyun const u8 *frame,
343*4882a593Smuzhiyun ssize_t len)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /*
348*4882a593Smuzhiyun * Parade's frames contains 32 bytes of data, divided
349*4882a593Smuzhiyun * into 4 frames:
350*4882a593Smuzhiyun * Token byte (first byte of first frame, must be non-zero)
351*4882a593Smuzhiyun * HB0 to HB2 from AVI IF (3 bytes header)
352*4882a593Smuzhiyun * PB0 to PB27 from AVI IF (28 bytes data)
353*4882a593Smuzhiyun * So it should look like this
354*4882a593Smuzhiyun * first block: | <token> <HB0-HB2> <DB0-DB3> |
355*4882a593Smuzhiyun * next 3 blocks: |<DB4-DB11>|<DB12-DB19>|<DB20-DB28>|
356*4882a593Smuzhiyun */
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
359*4882a593Smuzhiyun DRM_ERROR("Invalid length of infoframes\n");
360*4882a593Smuzhiyun return false;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun memcpy(&avi_if[1], frame, len);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
366*4882a593Smuzhiyun DRM_DEBUG_KMS("Failed to write infoframe blocks\n");
367*4882a593Smuzhiyun return false;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun return true;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
_lspcon_write_avi_infoframe_mca(struct drm_dp_aux * aux,const u8 * buffer,ssize_t len)373*4882a593Smuzhiyun static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
374*4882a593Smuzhiyun const u8 *buffer, ssize_t len)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun int ret;
377*4882a593Smuzhiyun u32 val = 0;
378*4882a593Smuzhiyun u32 retry;
379*4882a593Smuzhiyun u16 reg;
380*4882a593Smuzhiyun const u8 *data = buffer;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
383*4882a593Smuzhiyun while (val < len) {
384*4882a593Smuzhiyun /* DPCD write for AVI IF can fail on a slow FW day, so retry */
385*4882a593Smuzhiyun for (retry = 0; retry < 5; retry++) {
386*4882a593Smuzhiyun ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);
387*4882a593Smuzhiyun if (ret == 1) {
388*4882a593Smuzhiyun break;
389*4882a593Smuzhiyun } else if (retry < 4) {
390*4882a593Smuzhiyun mdelay(50);
391*4882a593Smuzhiyun continue;
392*4882a593Smuzhiyun } else {
393*4882a593Smuzhiyun DRM_ERROR("DPCD write failed at:0x%x\n", reg);
394*4882a593Smuzhiyun return false;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun val++; reg++; data++;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun val = 0;
401*4882a593Smuzhiyun reg = LSPCON_MCA_AVI_IF_CTRL;
402*4882a593Smuzhiyun ret = drm_dp_dpcd_read(aux, reg, &val, 1);
403*4882a593Smuzhiyun if (ret < 0) {
404*4882a593Smuzhiyun DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
405*4882a593Smuzhiyun return false;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */
409*4882a593Smuzhiyun val &= ~LSPCON_MCA_AVI_IF_HANDLED;
410*4882a593Smuzhiyun val |= LSPCON_MCA_AVI_IF_KICKOFF;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ret = drm_dp_dpcd_write(aux, reg, &val, 1);
413*4882a593Smuzhiyun if (ret < 0) {
414*4882a593Smuzhiyun DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
415*4882a593Smuzhiyun return false;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun val = 0;
419*4882a593Smuzhiyun ret = drm_dp_dpcd_read(aux, reg, &val, 1);
420*4882a593Smuzhiyun if (ret < 0) {
421*4882a593Smuzhiyun DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
422*4882a593Smuzhiyun return false;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (val == LSPCON_MCA_AVI_IF_HANDLED)
426*4882a593Smuzhiyun DRM_DEBUG_KMS("AVI IF handled by FW\n");
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return true;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
lspcon_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)431*4882a593Smuzhiyun void lspcon_write_infoframe(struct intel_encoder *encoder,
432*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
433*4882a593Smuzhiyun unsigned int type,
434*4882a593Smuzhiyun const void *frame, ssize_t len)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun bool ret;
437*4882a593Smuzhiyun struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
438*4882a593Smuzhiyun struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun /* LSPCON only needs AVI IF */
441*4882a593Smuzhiyun if (type != HDMI_INFOFRAME_TYPE_AVI)
442*4882a593Smuzhiyun return;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (lspcon->vendor == LSPCON_VENDOR_MCA)
445*4882a593Smuzhiyun ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
446*4882a593Smuzhiyun frame, len);
447*4882a593Smuzhiyun else
448*4882a593Smuzhiyun ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
449*4882a593Smuzhiyun frame, len);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun if (!ret) {
452*4882a593Smuzhiyun DRM_ERROR("Failed to write AVI infoframes\n");
453*4882a593Smuzhiyun return;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
lspcon_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)459*4882a593Smuzhiyun void lspcon_read_infoframe(struct intel_encoder *encoder,
460*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
461*4882a593Smuzhiyun unsigned int type,
462*4882a593Smuzhiyun void *frame, ssize_t len)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun /* FIXME implement this */
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
lspcon_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)467*4882a593Smuzhiyun void lspcon_set_infoframes(struct intel_encoder *encoder,
468*4882a593Smuzhiyun bool enable,
469*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
470*4882a593Smuzhiyun const struct drm_connector_state *conn_state)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun ssize_t ret;
473*4882a593Smuzhiyun union hdmi_infoframe frame;
474*4882a593Smuzhiyun u8 buf[VIDEO_DIP_DATA_SIZE];
475*4882a593Smuzhiyun struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
476*4882a593Smuzhiyun struct intel_lspcon *lspcon = &dig_port->lspcon;
477*4882a593Smuzhiyun const struct drm_display_mode *adjusted_mode =
478*4882a593Smuzhiyun &crtc_state->hw.adjusted_mode;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun if (!lspcon->active) {
481*4882a593Smuzhiyun DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
482*4882a593Smuzhiyun return;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* FIXME precompute infoframes */
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
488*4882a593Smuzhiyun conn_state->connector,
489*4882a593Smuzhiyun adjusted_mode);
490*4882a593Smuzhiyun if (ret < 0) {
491*4882a593Smuzhiyun DRM_ERROR("couldn't fill AVI infoframe\n");
492*4882a593Smuzhiyun return;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
496*4882a593Smuzhiyun if (crtc_state->lspcon_downsampling)
497*4882a593Smuzhiyun frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
498*4882a593Smuzhiyun else
499*4882a593Smuzhiyun frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
500*4882a593Smuzhiyun } else {
501*4882a593Smuzhiyun frame.avi.colorspace = HDMI_COLORSPACE_RGB;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun drm_hdmi_avi_infoframe_quant_range(&frame.avi,
505*4882a593Smuzhiyun conn_state->connector,
506*4882a593Smuzhiyun adjusted_mode,
507*4882a593Smuzhiyun crtc_state->limited_color_range ?
508*4882a593Smuzhiyun HDMI_QUANTIZATION_RANGE_LIMITED :
509*4882a593Smuzhiyun HDMI_QUANTIZATION_RANGE_FULL);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
512*4882a593Smuzhiyun if (ret < 0) {
513*4882a593Smuzhiyun DRM_ERROR("Failed to pack AVI IF\n");
514*4882a593Smuzhiyun return;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI,
518*4882a593Smuzhiyun buf, ret);
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
lspcon_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)521*4882a593Smuzhiyun u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
522*4882a593Smuzhiyun const struct intel_crtc_state *pipe_config)
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun /* FIXME actually read this from the hw */
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
lspcon_resume(struct intel_lspcon * lspcon)528*4882a593Smuzhiyun void lspcon_resume(struct intel_lspcon *lspcon)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun enum drm_lspcon_mode expected_mode;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun if (lspcon_wake_native_aux_ch(lspcon)) {
533*4882a593Smuzhiyun expected_mode = DRM_LSPCON_MODE_PCON;
534*4882a593Smuzhiyun lspcon_resume_in_pcon_wa(lspcon);
535*4882a593Smuzhiyun } else {
536*4882a593Smuzhiyun expected_mode = DRM_LSPCON_MODE_LS;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON)
540*4882a593Smuzhiyun return;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
543*4882a593Smuzhiyun DRM_ERROR("LSPCON resume failed\n");
544*4882a593Smuzhiyun else
545*4882a593Smuzhiyun DRM_DEBUG_KMS("LSPCON resume success\n");
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
lspcon_wait_pcon_mode(struct intel_lspcon * lspcon)548*4882a593Smuzhiyun void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON);
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
lspcon_init(struct intel_digital_port * dig_port)553*4882a593Smuzhiyun bool lspcon_init(struct intel_digital_port *dig_port)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun struct intel_dp *dp = &dig_port->dp;
556*4882a593Smuzhiyun struct intel_lspcon *lspcon = &dig_port->lspcon;
557*4882a593Smuzhiyun struct drm_device *dev = dig_port->base.base.dev;
558*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(dev);
559*4882a593Smuzhiyun struct drm_connector *connector = &dp->attached_connector->base;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun if (!HAS_LSPCON(dev_priv)) {
562*4882a593Smuzhiyun DRM_ERROR("LSPCON is not supported on this platform\n");
563*4882a593Smuzhiyun return false;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun lspcon->active = false;
567*4882a593Smuzhiyun lspcon->mode = DRM_LSPCON_MODE_INVALID;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if (!lspcon_probe(lspcon)) {
570*4882a593Smuzhiyun DRM_ERROR("Failed to probe lspcon\n");
571*4882a593Smuzhiyun return false;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun if (drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd) != 0) {
575*4882a593Smuzhiyun DRM_ERROR("LSPCON DPCD read failed\n");
576*4882a593Smuzhiyun return false;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun if (!lspcon_detect_vendor(lspcon)) {
580*4882a593Smuzhiyun DRM_ERROR("LSPCON vendor detection failed\n");
581*4882a593Smuzhiyun return false;
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun connector->ycbcr_420_allowed = true;
585*4882a593Smuzhiyun lspcon->active = true;
586*4882a593Smuzhiyun DRM_DEBUG_KMS("Success: LSPCON init\n");
587*4882a593Smuzhiyun return true;
588*4882a593Smuzhiyun }
589