1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __INTEL_HDMI_H__ 7*4882a593Smuzhiyun #define __INTEL_HDMI_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/hdmi.h> 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "i915_reg.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct drm_connector; 15*4882a593Smuzhiyun struct drm_encoder; 16*4882a593Smuzhiyun struct drm_i915_private; 17*4882a593Smuzhiyun struct intel_connector; 18*4882a593Smuzhiyun struct intel_digital_port; 19*4882a593Smuzhiyun struct intel_encoder; 20*4882a593Smuzhiyun struct intel_crtc_state; 21*4882a593Smuzhiyun struct intel_hdmi; 22*4882a593Smuzhiyun struct drm_connector_state; 23*4882a593Smuzhiyun union hdmi_infoframe; 24*4882a593Smuzhiyun enum port; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, 27*4882a593Smuzhiyun enum port port); 28*4882a593Smuzhiyun void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 29*4882a593Smuzhiyun struct intel_connector *intel_connector); 30*4882a593Smuzhiyun struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder); 31*4882a593Smuzhiyun int intel_hdmi_compute_config(struct intel_encoder *encoder, 32*4882a593Smuzhiyun struct intel_crtc_state *pipe_config, 33*4882a593Smuzhiyun struct drm_connector_state *conn_state); 34*4882a593Smuzhiyun bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 35*4882a593Smuzhiyun struct drm_connector *connector, 36*4882a593Smuzhiyun bool high_tmds_clock_ratio, 37*4882a593Smuzhiyun bool scrambling); 38*4882a593Smuzhiyun void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); 39*4882a593Smuzhiyun void intel_infoframe_init(struct intel_digital_port *dig_port); 40*4882a593Smuzhiyun u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 41*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 42*4882a593Smuzhiyun u32 intel_hdmi_infoframe_enable(unsigned int type); 43*4882a593Smuzhiyun void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 44*4882a593Smuzhiyun struct intel_crtc_state *crtc_state); 45*4882a593Smuzhiyun void intel_read_infoframe(struct intel_encoder *encoder, 46*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state, 47*4882a593Smuzhiyun enum hdmi_infoframe_type type, 48*4882a593Smuzhiyun union hdmi_infoframe *frame); 49*4882a593Smuzhiyun bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 50*4882a593Smuzhiyun const struct drm_connector_state *conn_state); 51*4882a593Smuzhiyun bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc, 52*4882a593Smuzhiyun bool has_hdmi_sink, bool ycbcr420_output); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* __INTEL_HDMI_H__ */ 55