1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright © 2013 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun * Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #ifndef _INTEL_DSI_H
25*4882a593Smuzhiyun #define _INTEL_DSI_H
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <drm/drm_crtc.h>
28*4882a593Smuzhiyun #include <drm/drm_mipi_dsi.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "intel_display_types.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define INTEL_DSI_VIDEO_MODE 0
33*4882a593Smuzhiyun #define INTEL_DSI_COMMAND_MODE 1
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Dual Link support */
36*4882a593Smuzhiyun #define DSI_DUAL_LINK_NONE 0
37*4882a593Smuzhiyun #define DSI_DUAL_LINK_FRONT_BACK 1
38*4882a593Smuzhiyun #define DSI_DUAL_LINK_PIXEL_ALT 2
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct intel_dsi_host;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct intel_dsi {
43*4882a593Smuzhiyun struct intel_encoder base;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
46*4882a593Smuzhiyun intel_wakeref_t io_wakeref[I915_MAX_PORTS];
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* GPIO Desc for panel and backlight control */
49*4882a593Smuzhiyun struct gpio_desc *gpio_panel;
50*4882a593Smuzhiyun struct gpio_desc *gpio_backlight;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct intel_connector *attached_connector;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
55*4882a593Smuzhiyun union {
56*4882a593Smuzhiyun u16 ports; /* VLV DSI */
57*4882a593Smuzhiyun u16 phys; /* ICL DSI */
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* if true, use HS mode, otherwise LP */
61*4882a593Smuzhiyun bool hs;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* virtual channel */
64*4882a593Smuzhiyun int channel;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Video mode or command mode */
67*4882a593Smuzhiyun u16 operation_mode;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* number of DSI lanes */
70*4882a593Smuzhiyun unsigned int lane_count;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* i2c bus associated with the slave device */
73*4882a593Smuzhiyun int i2c_bus_num;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * video mode pixel format
77*4882a593Smuzhiyun *
78*4882a593Smuzhiyun * XXX: consolidate on .format in struct mipi_dsi_device.
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun enum mipi_dsi_pixel_format pixel_format;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
83*4882a593Smuzhiyun u32 video_mode_format;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* eot for MIPI_EOT_DISABLE register */
86*4882a593Smuzhiyun u8 eotp_pkt;
87*4882a593Smuzhiyun u8 clock_stop;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun u8 escape_clk_div;
90*4882a593Smuzhiyun u8 dual_link;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun u16 dcs_backlight_ports;
93*4882a593Smuzhiyun u16 dcs_cabc_ports;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* RGB or BGR */
96*4882a593Smuzhiyun bool bgr_enabled;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun u8 pixel_overlap;
99*4882a593Smuzhiyun u32 port_bits;
100*4882a593Smuzhiyun u32 bw_timer;
101*4882a593Smuzhiyun u32 dphy_reg;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* data lanes dphy timing */
104*4882a593Smuzhiyun u32 dphy_data_lane_reg;
105*4882a593Smuzhiyun u32 video_frmt_cfg_bits;
106*4882a593Smuzhiyun u16 lp_byte_clk;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* timeouts in byte clocks */
109*4882a593Smuzhiyun u16 hs_tx_timeout;
110*4882a593Smuzhiyun u16 lp_rx_timeout;
111*4882a593Smuzhiyun u16 turn_arnd_val;
112*4882a593Smuzhiyun u16 rst_timer_val;
113*4882a593Smuzhiyun u16 hs_to_lp_count;
114*4882a593Smuzhiyun u16 clk_lp_to_hs_count;
115*4882a593Smuzhiyun u16 clk_hs_to_lp_count;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun u16 init_count;
118*4882a593Smuzhiyun u32 pclk;
119*4882a593Smuzhiyun u16 burst_mode_ratio;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* all delays in ms */
122*4882a593Smuzhiyun u16 backlight_off_delay;
123*4882a593Smuzhiyun u16 backlight_on_delay;
124*4882a593Smuzhiyun u16 panel_on_delay;
125*4882a593Smuzhiyun u16 panel_off_delay;
126*4882a593Smuzhiyun u16 panel_pwr_cycle_delay;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun struct intel_dsi_host {
130*4882a593Smuzhiyun struct mipi_dsi_host base;
131*4882a593Smuzhiyun struct intel_dsi *intel_dsi;
132*4882a593Smuzhiyun enum port port;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* our little hack */
135*4882a593Smuzhiyun struct mipi_dsi_device *device;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
to_intel_dsi_host(struct mipi_dsi_host * h)138*4882a593Smuzhiyun static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun return container_of(h, struct intel_dsi_host, base);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define for_each_dsi_port(__port, __ports_mask) \
144*4882a593Smuzhiyun for_each_port_masked(__port, __ports_mask)
145*4882a593Smuzhiyun #define for_each_dsi_phy(__phy, __phys_mask) \
146*4882a593Smuzhiyun for_each_phy_masked(__phy, __phys_mask)
147*4882a593Smuzhiyun
enc_to_intel_dsi(struct intel_encoder * encoder)148*4882a593Smuzhiyun static inline struct intel_dsi *enc_to_intel_dsi(struct intel_encoder *encoder)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun return container_of(&encoder->base, struct intel_dsi, base.base);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
is_vid_mode(struct intel_dsi * intel_dsi)153*4882a593Smuzhiyun static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
is_cmd_mode(struct intel_dsi * intel_dsi)158*4882a593Smuzhiyun static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
intel_dsi_encoder_ports(struct intel_encoder * encoder)163*4882a593Smuzhiyun static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun return enc_to_intel_dsi(encoder)->ports;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* icl_dsi.c */
169*4882a593Smuzhiyun void icl_dsi_init(struct drm_i915_private *dev_priv);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* intel_dsi.c */
172*4882a593Smuzhiyun int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
173*4882a593Smuzhiyun int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
174*4882a593Smuzhiyun enum drm_panel_orientation
175*4882a593Smuzhiyun intel_dsi_get_panel_orientation(struct intel_connector *connector);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* vlv_dsi.c */
178*4882a593Smuzhiyun void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
179*4882a593Smuzhiyun enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
180*4882a593Smuzhiyun int intel_dsi_get_modes(struct drm_connector *connector);
181*4882a593Smuzhiyun enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
182*4882a593Smuzhiyun struct drm_display_mode *mode);
183*4882a593Smuzhiyun struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
184*4882a593Smuzhiyun const struct mipi_dsi_host_ops *funcs,
185*4882a593Smuzhiyun enum port port);
186*4882a593Smuzhiyun void vlv_dsi_init(struct drm_i915_private *dev_priv);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* vlv_dsi_pll.c */
189*4882a593Smuzhiyun int vlv_dsi_pll_compute(struct intel_encoder *encoder,
190*4882a593Smuzhiyun struct intel_crtc_state *config);
191*4882a593Smuzhiyun void vlv_dsi_pll_enable(struct intel_encoder *encoder,
192*4882a593Smuzhiyun const struct intel_crtc_state *config);
193*4882a593Smuzhiyun void vlv_dsi_pll_disable(struct intel_encoder *encoder);
194*4882a593Smuzhiyun u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
195*4882a593Smuzhiyun struct intel_crtc_state *config);
196*4882a593Smuzhiyun void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
199*4882a593Smuzhiyun int bxt_dsi_pll_compute(struct intel_encoder *encoder,
200*4882a593Smuzhiyun struct intel_crtc_state *config);
201*4882a593Smuzhiyun void bxt_dsi_pll_enable(struct intel_encoder *encoder,
202*4882a593Smuzhiyun const struct intel_crtc_state *config);
203*4882a593Smuzhiyun void bxt_dsi_pll_disable(struct intel_encoder *encoder);
204*4882a593Smuzhiyun u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
205*4882a593Smuzhiyun struct intel_crtc_state *config);
206*4882a593Smuzhiyun void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* intel_dsi_vbt.c */
209*4882a593Smuzhiyun bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
210*4882a593Smuzhiyun void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);
211*4882a593Smuzhiyun void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi);
212*4882a593Smuzhiyun void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
213*4882a593Smuzhiyun enum mipi_seq seq_id);
214*4882a593Smuzhiyun void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
215*4882a593Smuzhiyun void intel_dsi_log_params(struct intel_dsi *intel_dsi);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun #endif /* _INTEL_DSI_H */
218