xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/intel_dsb.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright © 2019 Intel Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _INTEL_DSB_H
7*4882a593Smuzhiyun #define _INTEL_DSB_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include "i915_reg.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct intel_crtc_state;
14*4882a593Smuzhiyun struct i915_vma;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun enum dsb_id {
17*4882a593Smuzhiyun 	INVALID_DSB = -1,
18*4882a593Smuzhiyun 	DSB1,
19*4882a593Smuzhiyun 	DSB2,
20*4882a593Smuzhiyun 	DSB3,
21*4882a593Smuzhiyun 	MAX_DSB_PER_PIPE
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct intel_dsb {
25*4882a593Smuzhiyun 	enum dsb_id id;
26*4882a593Smuzhiyun 	u32 *cmd_buf;
27*4882a593Smuzhiyun 	struct i915_vma *vma;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	/*
30*4882a593Smuzhiyun 	 * free_pos will point the first free entry position
31*4882a593Smuzhiyun 	 * and help in calculating tail of command buffer.
32*4882a593Smuzhiyun 	 */
33*4882a593Smuzhiyun 	int free_pos;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	/*
36*4882a593Smuzhiyun 	 * ins_start_offset will help to store start address of the dsb
37*4882a593Smuzhiyun 	 * instuction and help in identifying the batch of auto-increment
38*4882a593Smuzhiyun 	 * register.
39*4882a593Smuzhiyun 	 */
40*4882a593Smuzhiyun 	u32 ins_start_offset;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
44*4882a593Smuzhiyun void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
45*4882a593Smuzhiyun void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
46*4882a593Smuzhiyun 			 i915_reg_t reg, u32 val);
47*4882a593Smuzhiyun void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
48*4882a593Smuzhiyun 				 i915_reg_t reg, u32 val);
49*4882a593Smuzhiyun void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #endif
52